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PDF SAA7130HL Data sheet ( Hoja de datos )
| Número de pieza | SAA7130HL | |
| Descripción | PCI video broadcast decoder | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7130HL
PCI video broadcast decoder
Product specification
2002 Apr 23
1 page  
Philips Semiconductors
PCI video broadcast decoder
Product specification
SAA7130HL
2.2 Overview of TV decoders with PCI bridge
A TV decoder family with PCI interfacing has been created to support worldwide TV broadcasting. The pin compatibility
of these TV decoders offers the opportunity to support different TV broadcast standards with one PCB layout.
Table 1 TV decoder family with PCI interfacing
TV PARAMETER
TV DECODER TYPE(1)
SAA7130HL SAA7133HL SAA7134HL SAA7135HL
PCI bridge
TV video decoding
Video scaling
Raw VBI
TV sound decoding
Radio
Audio
Transport stream
GPIO
version
DMA channel
PAL, NTSC and SECAM
2 dimension and 2 task scaler
27 MHz sampling rate
FM A2 and NICAM
BTSC (dBx) plus SAP; EIAJ
stereo sampling
(I2S-bus and DMA)
FM radio stereo
left and right pass-through
stereo sampling
(I2S-bus and DMA)
video frame locked audio
incredible surround
Dolby® Prologic (note 2)
virtual Dolby® surround
volume, bass and treble
control
serial and parallel TS
static I/O pins
interrupt input pins
I2C-bus multi-master or slave
video out
2.2
7
X
X
X
X
X
27
4
X
X
2.2
7
X
X
X
X
32 kHz
X
X
32 kHz,
44.1 kHz,
48 kHz
X
X
X
2.2
7
X
X
X
X
32 kHz,
48 kHz
X
32 kHz,
44.1 kHz,
48 kHz
X
X
volume only
2.2
7
X
X
X
X
X
32 kHz,
48 kHz
X
X
32 kHz,
44.1 kHz,
48 kHz
X
X
X
X
X
XXX
27 27 27
444
XXX
XXX
Notes
1. X = function available.
2. Dolby is a registered trademark of Dolby Laboratories Licensing Corporation.
2002 Apr 23
5
5 Page 
Philips Semiconductors
PCI video broadcast decoder
Product specification
SAA7130HL
SYMBOL
PIN TYPE
DESCRIPTION
INT_A
PERR#
SERR#
126 PO and interrupt A output: this pin is an open-drain interrupt output, conditions
O/D assigned by the interrupt register
30 PIO and parity error input or output: the receiving device detects data parity error
S/T/S (active LOW)
31 PO and system error output: reports address parity error (active LOW)
O/D
Note
1. PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements.
Table 4 Analog interface pins; note 1
SYMBOL
XTALI
XTALO
LEFT2
VDDA
LEFT1
VSSA
RIGHT1
VREF0
RIGHT2
n.c.
n.c.
OUT_RIGHT
OUT_LEFT
PROP_RST
n.c.
VREF3
VSSA
CV2_C
VDDA
n.c.
DRCV_Y
VSSA
CV0_Y
VDDA
PIN TYPE
DESCRIPTION
62 CI
quartz oscillator input: 32.11 or 24.576 MHz
63 CO quartz oscillator output
94 AI
analog audio stereo left 2 input or mono input
95 AS analog supply voltage (3.3 V)
96 AI
analog audio stereo left 1 input or mono input; default analog pass-through
to pin OUT_LEFT after reset
97 AG analog ground (for audio)
98 AI
analog audio stereo right 1 input or mono input; default analog pass-through
to pin OUT_RIGHT after reset
99 AR
100 AI
analog reference ground for audio Sigma Delta ADC; to be connected
directly to analog ground (VSSA)
analog audio stereo right 2 input or mono input
101 −
not connected
102 −
not connected
103 AO analog audio stereo right channel output; 1 V (RMS) line-out, feeding the
audio loop back cable via a coupling capacitor of 2.2 µF
104 AO analog audio stereo left channel output; 1 V (RMS) line-out, feeding the
audio loop back cable via a coupling capacitor of 2.2 µF
105 AO analog output for test and debug purpose (active LOW)
106 −
not connected
107 AR
analog reference voltage for audio FIR-DAC and SCART audio input buffer;
to be supported with two parallel capacitors of 47 and 0.1 µF to analog
ground (VSSA)
108 AG analog ground
109 AI
composite video input (mode 2) or C input (modes 6 and 8)
110 AS
analog power supply (3.3 V)
111 −
not connected
112 AR differential reference connection (for CV0 and CV1); to be supported with a
capacitor of 47 nF to analog ground (VSSA)
113 AG analog ground
114 AI
composite video input (mode 0) or Y input (modes 6 and 8)
115 AS
analog supply voltage (3.3 V)
2002 Apr 23
11
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