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PDF SHC5320KH Data sheet ( Hoja de datos )
| Número de pieza | SHC5320KH | |
| Descripción | High-Speed/ Bipolar/ Monolithic SAMPLE/HOLD AMPLIFIER | |
| Fabricantes | Burr-Brown Corporation | |
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® SHC5320
For most current data sheet and other product
information, visit www.burr-brown.com
FPO
High-Speed, Bipolar, Monolithic
SAMPLE/HOLD AMPLIFIER
FEATURES
q ACQUISITION TIME TO 0.01%: 1.5µs max
q HOLD MODE SETTLING TIME: 350ns max
q DROOP RATE AT +25°C: 0.5µV/µs max
q TTL COMPATIBLE
q FULL DIFFERENTIAL INPUTS
q INTERNAL HOLDING CAPACITOR
q TWO TEMPERATURE RANGES:
–40°C to +85°C (KH, KP, KU)
–55°C to +125°C (SH)
q PACKAGE OPTIONS: Ceramic and Plastic
DIP-14, SO-16
APPLICATIONS
q PRECISION DATA ACQUISITION
SYSTEMS
q DIGITAL-TO-ANALOG CONVERTER
DEGLITCHER
q AUTO ZERO CIRCUITS
q PEAK DETECTORS
Offset
Adjust
–Input
+Input
Mode
Control
External
Hold
Capacitor
100pF
–
Output
+
Reference Bandwidth
Common Control
DESCRIPTION
The SHC5320 is a bipolar, monolithic, sample/hold
circuit designed for use in precision, high-speed, data-
acquisition applications.
The circuit employs an input transconductance ampli-
fier capable of providing large amounts of charging
current to the holding capacitor, thus enabling fast
acquisition times. It also incorporates a low leakage
analog switch and an output integrating amplifier with
input bias current optimized to assure low droop rates.
Since the analog switch always drives into a load at
virtual ground, charge injection into the holding ca-
pacitor is constant over the entire input voltage range.
As a result, the charge offset (pedestal voltage) result-
ing from this charge injection can be adjusted to zero
by use of the offset adjustment capability. The device
includes an internal holding capacitor to simplify ease
of application; however, provision is also made to add
additional external capacitance to improve the output
voltage droop rate.
The SHC5320 is manufactured using a dielectric iso-
lation process which minimizes stray capacitance (en-
abling higher-speed operation), and eliminates latch-
up associated with substrate SCRs. The SHC5320KH,
KP, and KU feature fully specified operation over the
extended industrial temperature range of –40°C to
+85°C, while the SHC5320SH operates over the tem-
perature range of –55°C to +125°C. The device re-
quires ±15V supplies for operation, and is packaged in
a reliable 14-pin ceramic or plastic dual-in-line pack-
age, as well as a 16-pin surface mount plastic package.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1985 Burr-Brown Corporation
PDS1-585G
SPHrinCte5d i3n2U0.S.A. April, 2000
®
1 page  
DISCUSSION OF
SPECIFICATIONS
WHAT IS A SAMPLE/HOLD AMPLIFIER?
A sample/hold amplifier (also sometimes called a track-and-
hold amplifier) is a circuit that captures and holds an analog
voltage at a specific point in time under control of an
external circuit, such as a microprocessor. This type of
circuit has many applications; however, its primary use is in
data acquisition systems which require that the voltage be
captured and held during the analog-to-digital conversion
process. Use of a sample/hold effectively increases the
bandwidth of a data acquisition system by a significant
amount. For further discussion of this capability, refer to
“Signal Digitization” in the Applications section of this data
sheet.
The ideal sample/hold amplifier in its simplest form contains
four primary components as illustrated in Figure 1, although
in actual practice they may not be internally connected
exactly as shown. Amplifier A1, the input buffer, provides a
high impedance load to the source circuit and supplies
charging current to the holding capacitor CH. Switch S1
opens and closes under external control to gate the buffered
input signal to the holding circuit or to remove it so that the
most recently sampled signal will be held. Amplifier A2
serves to present a high impedance load to the holding
capacitor and to provide a low impedance voltage source for
external loads. A minimum of three terminals are provided
for the user: input, output, and mode control (or sample/hold
control). When S1, is closed, the output signal follows the
input signal, subject to errors imposed by amplifier band-
width and other errors as discussed below. When S , is
1
opened, the voltage stored on the holding capacitor will be
held indefinitely (in the ideal case), and will appear at the
output of the circuit until S1, is again closed under command
of the mode control signal.
Input
Mode
Control
–
A1
+
–
S1 A2
+ Output
CH
FIGURE 1. Ideal Sample/Hold Amplifier.
The following discussion of specifications covers the critical
types of errors which may be experienced in applications of
a sample/hold amplifier. These errors are depicted graphi-
cally in Figure 2, and in the Typical Performance Curves.
Acquisition Time is the time required for the sample/hold
output to settle within a given error band of its final value
after the sample mode is initiated. Included in this time are
effects of switch delay time, slew rate of the buffer ampli-
fier, and settling time for a specified change in held voltage
value. Slew rate limitations of the buffer amplifier will cause
Settling
Time
Sample-to-Hold
Transient and
Charge Offset
Input
Feed-
though
Output
Droop
Offset
Aperture
Uncertainty
Aperture Time Acquisition
Hold
Time
Sample Mode Control
Slew Rate
Limited
Settling
Time
Sample
FIGURE 2. Illustration of Sample/Hold Specifications.
actual acquisition time to be highly dependent on the ampli-
tude of the voltage to be acquired, relative to the value
already held by the capacitor. Therefore, proper specifica-
tion of sample/hold amplifier performance includes defini-
tion of both output value step size and required error band
accuracy.
Aperture Time (or aperture delay time) is the time required
for switch S , to open and remove the charging signal from
1
the capacitor after the mode control signal has changed from
“sample” to “hold.” This time is measured from the 50%
point of the Hold mode transition to the time at which the
output stops tracking the input. This parameter is very
important in applications for which the input signal is
changing very rapidly when the Hold mode is initiated.
Effective Aperture Time is the difference in propagation
delay times of the analog signal and the mode control signal
from their respective input pins to switch S1. This time may
be negative, zero, or positive. A negative value indicates that
the mode control propagation delay is shorter than the
analog propagation delay, with the result that the analog
value present on the capacitor at the time the switch opens
occurred earlier than the application of the mode control
signal by the amount of the effective aperture delay time.
Aperture Uncertainty (or aperture jitter) is the variation
observed in the aperture time over a large number of obser-
vations. This parameter is important when the analog input
is a rapidly changing signal, as aperture uncertainty contrib-
utes to lack of knowledge (at the output) about the true value
of the input at the precise time the Hold mode is initiated.
The maximum input frequency for a given acceptable error
contribution due to aperture uncertainty is
fMAX = Maximum Fractional Error/2πtU
where Maximum Fractional Error (MFE) is the ratio of the
maximum allowable error voltage to peak voltage, and tU is
the aperture uncertainty time. For a bipolar ±10V signal and
a maximum uncertainty error of 1/2LSB in a 12-bit system,
the MFE is equal to 1/2LSB ÷ VPEAK = 2.44mV ÷ 10V =
0.000244V/V, since 1/2LSB = 2.44mV for a 20V full-scale
range.
For the same system operating with a unipolar 0V to 10V
signal, MFE would be 0.000122V/V.
®
5 SHC5320
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