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PDF SL4053BN Data sheet ( Hoja de datos )
| Número de pieza | SL4053BN | |
| Descripción | Analog Multiplexer Demultiplexer | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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Analog Multiplexer Demultiplexer
SL4053B
High-Performance Silicon-Gate CMOS
The SL4053B analog multiplexer/demultiplexer is digitally controlled
analog switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-to-peak can be
achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a
VCC - VEE of up to 13 V can be controlled; for VCC - VEE level differences
above 13V a VCC - GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full VCC -GND and VCC - VEE supply-voltage ranges,
independent of the logic state of the control signals. When a logic
“1”is present at the ENABLE input terminal all channels are off.
The SL4053B is a triple 2-channel multiplexer having three separate
digital control inputs, A, B, and C, and an enable input. Each control
input selects one of a pair of channels which are connected in a single-
pole double-throw configuration.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4053BN Plastic
SL4053BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND
SLS
System Logic
Semiconductor
FUNCTION TABLE
Control Inputs
Enable
Select
C BA
L LLL
L L LH
L LHL
L L HH
L HLL
L H LH
L HHL
L HHH
H XXX
X = don’t care
ON
Channels
Z0 Y0
Z0 Y0
Z0 Y1
Z0 Y1
Z1 Y0
Z1 Y0
Z1 Y1
Z1 Y1
None
X0
X1
X0
X1
X0
X1
X0
X1
1 page  
SL4053B
ADDITIONAL APPLICATION CHARACTERISTICS
Symbol
BW
THD
Parameter
Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response (-3db)
(-40db)
Feedthrough
Frequency (All
Channels OFF)
(-40db)
Signal Crosstalk
Frequency
Total Harmonic
Distortion
Test Conditions
VEE=GND
RL=1kΩ
20 log(VOS/VIS)=-3db
VOS at Common OUT/IN
VOS at Any Channel
VEE=GND
RL=1kΩ
20 log(VOS/VIS)=-40db
VOS at Common OUT/IN
VOS at Any Channel
VEE=GND
RL=1kΩ
20 log(VOS/VIS)=-40db
Between any 2 Sections :
In Pin 2, Out Pin 14
In Pin 15, Out Pin 14
VEE=GND
fIS=1kHz sine wave
- Address-or
VEE=GND
Enable to Signal RL=10kΩ**
Crosstalk
tr,tf=20ns
Square Wave
* Peak-to-peak voltage symmetrical about (VDD-VEE)/2
**Both ends of channel
VCC VIS Limit*
V V 25 °C Unit
10 5* 30 MHz
10 5* 60
10 5*
10 5*
8
8
2.5
6
5 2* 0.3 %
10 3* 0.2
15 5* 012
10 - 65 mv
(peak)
SLS
System Logic
Semiconductor
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet SL4053BN.PDF ] | |
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