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PDF SL4017BN Data sheet ( Hoja de datos )
| Número de pieza | SL4017BN | |
| Descripción | Counter/Divider | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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SL4017B
Counter/Divider
High-Voltage Silicon-Gate CMOS
The SL4017B is 5-stage Johnson counter having 10
decoded outputs. Inputs include a CLOCK, a RESET, and a
CLOCK INHIBIT signal. Schmitt trigger action in the
CLOCK input circuit provides pulse shaping that allows
unlimited clock input pulse rise and fall times.
The counter is advanced one count at the positive
clock signal transition if the CLOCK INHIBIT signal is
low. Counter advancement via the clock line is inhibited
when the CLOCK INHIBIT signal is high. A high RESET
signal clears the counter to its zero count. Use of the
Johnson counter configuration permits high-speed
operation, 2-input decode-gating and spike-free decoded
outputs. Anti-lock gating is provided, thus assuring proper
counting sequence. The decoded outputs are normally low
and go high only at their respective decoded time slot.
Each decoded output remains high for one full clock cycle.
A CARRY-OUT signal completes one cycle every 10 clock
input cycles in the SL4017B.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full
package-temperature range; 100 nA at 18 V and 25°C
ORDERING INFORMATION
SL4017BN Plastic
SL4017BD SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
• Noise margin (over full package
temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
PIN 16 =VCC
PIN 8 = GND
SL System Logic
S Semiconductor
1 page  
SL4017B
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
Symbol
Parameter
fmax Maximum Clock Frequency
tPLH, tPHL Maximum Propagation Delay, Clock to
Decode Output (Figure 1)
tPLH, tPHL Maximum Propagation Delay, Clock to
Carry Output (Figure 1)
tTLH, tTHL
Maximum Output Transition Time,
Carry Output or Decode Output (Figure
1)
tPLH, tPHL
Maximum Propagation Delay, Reset to
Carry Output or Decode Output (Figure
1)
CIN Maximum Input Capacitance
VCC Guaranteed Limit
V ≥-55°C 25°C ≤125°
C
5.0 2.5
10 5
15 5.5
2.5 1.25
5 2.5
5.5 2.75
5.0 650
10 270
15 170
650 1300
270 540
170 340
5.0 600
10 250
15 160
600 1200
250 500
160 320
5.0 200 200 400
10 100 100 200
15 80
80 160
5.0 530
10 230
15 170
530 1060
230 460
170 340
-5
Unit
MHz
ns
ns
ns
ns
pF
TIMING REQUIREMENTS (VCC=5.0V±10%, CL=50pF, Input tr=tf=20 ns, RL=200kΩ )
VCC Guaranteed Limit
Symbol
Parameter
V ≥-55°C 25°C ≤125°
C
tw Minimum Pulse Width, Clock (Figure 1) 5.0 200 200 400
10 90
90 180
15 60
60 120
tr, tf Maximum Input Rise and Fall Times, 5.0
Clock (Figure 1)
10
15
UNLIMITED
tw Minimum Pulse Width, Reset (Figure 5.0 260 260 520
1) 10 110 110 220
15 60
60 120
trem Minimum Removal Time, Reset
(Figure 1)
5.0 400 400 800
10 280 280 560
15 150 150 300
Unit
ns
µs
ns
ns
SL System Logic
S Semiconductor
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SL4017BN.PDF ] | |
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