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PDF SL2101CKG Data sheet ( Hoja de datos )
| Número de pieza | SL2101CKG | |
| Descripción | Synthesized Broadband Converter with Programmable Power | |
| Fabricantes | Zarlink Semiconductor Inc | |
| Logotipo |  |
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SL2101
Synthesized Broadband Converter with
Programmable Power
Data Sheet
Features
• Single chip synthesized broadband solution
• Configurable as both up converter and
downconverter requirements in double
conversion tuner applications
• Incorporates 8 programmable mixer power
settings
• Compatible with digital and analogue system
requirements
• CSO -65 dBc, CTB -68 dBc (typical)
• Extremely low phase noise balanced local
oscillator, with very low fundamental and
harmonic radiation
• PLL frequency synthesizer designed for high
comparison frequencies and low phase noise
• Buffered crystal output for pipelining system
reference frequency
• I2C Controlled
Applications
• Double conversion tuners
• Digital Terrestrial tuners
• Cable telephony
• Cable Modems
• MATV
Ordering Information
August 2004
SL2101C/KG/NP1P SSOP
SL2101C/KG/NP1Q SSOP
SL2101C/KG/NP2P SSOP*
SL2101C/KG/NP2Q SSOP*
SL2101C/KG/LH2N MLP*
SL2101C/KG/LH2Q MLP*
Tubes
Tape & Reel
Tubes
Tape & Reel
Trays
Tape& Reel
* Pb free
All codes baked and drypacked
-40°C to +85°C
Description
The SL2101 is a fully integrated single chip broadband
mixer oscillator with low phase noise PLL frequency
synthesizer. It is intended for use in double conversion
tuners as both the up and down converter and is
compatible with HIIF frequencies up to 1.4 GHz and all
standard tuner IF output frequencies. It also contains a
programmable power facility for use in systems where
power consumption is important.
The device contains all elements necessary, with the
exception of local oscillator tuning network, loop filter
and crystal reference to produce a complete
synthesized block converter, compatible with digital
and analogue requirements.
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
SL2101
Data Sheet
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in figure
23. Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Figure 25 is used when
driving a second SL2101 as a downconverter.
The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop
filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the
oscillator.
The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to
port P0 by programming the device into test mode. The test modes are described in Figure 26.
The crystal reference frequency can be switched to BUFREF output by bit RE as described in Figure 27. The
BUFREF output is not available on the MLP package.
Programming
The SL2101 is controlled by an I2C data bus and is compatible with both standard and fast mode formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is low, and read mode if it is high. Tables 1 and 2 in Figure 28 illustrate the format of the data. The
device can be programmed to respond to several addresses, which enables the use of more than one device in an
I2C bus system. Figure 28, Table 3 shows how the address is selected by applying a voltage to the 'ADD' input.
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are received. When the device is programmed into read
mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Write Mode
With reference to Figure 28, Table 1, bytes 2 and 3 contain frequency information bits 214 -20 inclusive.
Byte 4 controls the synthesizer reference divider ratio, see Figure 23 and the charge pump setting, see Figure 29.
Byte 5 controls the test modes, see Figure 26, the buffered crystal reference output select RE, see Figure 27, the
power setting, see Figure 7 and the output port P0.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows
the same procedure, without re-addressing the device. This procedure continues until a STOP condition is
received. The STOP condition can be generated after any data byte, if however it occurs during a byte
transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP
condition.
Read Mode
When the device is in read mode, the status byte read from the device takes the form shown in Figure 28, Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped
below 3V (at 25° C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is
terminated by a STOP command. When POR is set high this indicates that the programmed information may have
been corrupted and the device reset to the power up condition.
Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic
'0' if the device is unlocked.
5
Zarlink Semiconductor Inc.
5 Page 
SL2101
Data Sheet
11
10
9
8
7
6
5
4
3
2
1
0
0
Gain
100 200 300 400 500 600 700 800 900
Input frequency(in MHz)
Figure 14 - Conversion Gain as Upconverter (Maximum Power Setting)
I2
I1
I0
Typ NF
(dB)
Gain
(dB)
typ
CSO*
(dBc)
typ
CTB*
(dBc)
typ
IPIP2
(dBµV)
typ
IPIP3
(dBµV)
0 0 0 6.8 10.1 -65 -65 144 121
0 0 1 6.0 9.1 -60 -54 141 114
0 1 0 5.8 7.6 -56 -42 132 108
0 1 1 6.5 5.4 -49 -35 129 106
1 0 0 8.7 10.4 -63 -60 146 117
1 0 1 6.2 10.0 -64 -56 142 113
1 1 0 5.9 8.3 -58 -42 133 106
1 1 1 6.4 5.8 -50 -34 126 103
Figure 15 - Upconverter Gain, NF and Intermodulation with Recommended Load Versus Power
Setting
* Measured with 128 channels at +7 dBmV.
2 pF
BB555
1 kΩ
Varactor
line
3x0.5 mm
3x1.5 mm
BB555
3x2.75 mm
(centre)
Figure 16 - Upconverter Oscillator Application
11
Zarlink Semiconductor Inc.
11 Page | ||
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