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PDF SL1935 Data sheet ( Hoja de datos )
| Número de pieza | SL1935 | |
| Descripción | Single Chip Synthesized Zero IF Tuner | |
| Fabricantes | ETC | |
| Logotipo |  |
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SL1935
Single Chip Synthesized Zero IF Tuner
Features
• Single chip synthesised tuner solution for quadrature
down conversion, L-band to Zero IF.
• DVB compliant, operating dynamic range -70 to
-20dBm.
• Compatible with DSS and DVB variable symbol rate
applications.
• Selectable baseband path, programmable through
I2C bus.
• Excellent quadrature balance up to 30MHz
baseband
• Excellent immunity to spurious second harmonic
(RF and LO) mixing effects.
• Low oscillator phase noise and reradiation.
• High output referred linearity for low distortion and
multi channel application.
• Integral fast mode compliant I2C bus controlled PLL
frequency synthesiser, designed for high comparison
frequencies and low phase noise performance.
• Buffered crystal output for clocking QPSK
demodulator.
• ESD protection (Normal ESD handling procedures
should be observed).
Applications
• Satellite receiver systems.
• Data communications systems.
April 2004
Ordering Information
SL1935D/KG/NP1P (Tubes) 36 pin SSOP
SL1935D/KG/NP1Q (Tape and Reel) 36 pin SSOP
Description
The SL1935 is a complete single chip I2C bus controlled
Zero IF tuner and operates from 950 to 2150MHz. It
includes an on-board low phase noise PLL frequency
synthesiser and low noise LNA/AGC. The SL1935 is
intended primarilyfor application in digital satellite Network
Interface Modules and performs the complete tuner
function.
The device contains all elements necessary, with the
exception of local oscillator tuning network and crystal
reference, to produce a high performance I(n-phase) &
Q(uadrature) downconversion tuner function. Due to the
high signal handling design the device does not require
any front end tracking filters.
The SL1935 includes selectable baseband signal paths,
allowing application with two externally definable filter
bandwidths, facilitating application in variable symbol
rate and simulcast systems. The SL1935 is optimised to
interface with the VP310 (ADC/QPSK/FEC) Satellite
Channel Decoder, available from Zarlink Semiconductor
and offers a full front end solution.
XTALCAP
XTAL
SDA
SCL
BUFREF
VCCD
VCC
RF
RFB
VCC
IFIA
IFIB
VCC
OFIA
OFIB
VEE
IOUT
ADD
1
18
36 PUMP
DRIVE
PORT P0
VEE
TANKS
TANKSB
VEE
TANKV
TANKVB
VEE
IFQA
IFQB
VCC
OFQA
OFQB
VEE
QOUT
19 AGCCONT
Figure1. Pin connections
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
SL1935
The STOP condition can be generated after any data
byte, if however it occurs during a byte transmission, the
previous byte data is retained. To facilitate smooth fine
tuning, the frequency data bytes are only accepted by
the device after all 15 bits of frequency data have been
received, or after the generation of a STOP condition.
Read mode
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the Vccd supply to the device has dropped
below 3V (at 25oC),e.g. when the device is initially turned
ON. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates that the programmed information may
have been corrupted and the device reset to the power
up condition.
When the device is in read mode, the status byte read
from the device takes the form shown in Table 9b.
Bit 2 (FL) indicates whether the synthesiser is phase
locked, a logic ‘1’ is present if the device is locked, and
a logic ‘0’ if the device is unlocked.
Table 2. Programmable Features
Programmable features
Function
Synthesiser programmable divider
Reference programmable divider
Baseband filter path select
Local oscillator select
Charge pump current
Test mode
General purpose port, P0
Buffered crystal reference output,
BUFREF
Function as described above
Function as described above.
Function as described above.
Function as described above.
The charge pump current can be programmed by bits C1 & C0 (Table 5).
The test modes are defined by bits T2 - T0 as described in Table 4.
The general purpose port can be programmed by bit P0;
Logic ‘1’ = on
Logic ‘0’ = off (high impedance)
The buffered crystal reference frequency can be switched to the BUFREF
output by bit RE as described in Table 7. The BUFREF output defaults to
the ‘ON’ condition at device power up.
The typical key performance data at Vcc = 5V and +25oC ambient are detailed in Table 1.
Table 3. Reference division ratios
R4 R3 R2 R1
0 000
0 000
0 001
0 001
0 010
0 010
0 011
0 011
0 100
0 100
0 101
0 101
0 110
0 110
0 111
0 111
1 000
1 000
1 001
1 001
1 010
1 010
1 011
1 011
1 100
1 100
1 101
1 101
1 110
1 110
1 111
1 111
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ratio
2
4
8
16
32
64
128
256
Illegal state
5
10
20
40
80
160
320
Illegal state
6
12
24
48
96
192
384
Illegal state
7
14
28
56
112
224
448
5
5 Page 
SL1935
OFIA/OFIB
OFQA/OFQB
100nF
1k Ω
1k Ω
100nF
3.9pF
IFIA/IFIB
IFQA/IFQB
Figure 13. Example baseband interstage filter for 30MS/s
220nF
100 Ω
1k Ω
15pF
Figure 14. Nominal baseband output load test condition
82pF
150pF
4MHz
1 XTALCAP
2 XTAL
Figure 15. Crystal oscillator application (typical)
11
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet SL1935.PDF ] | |
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