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PDF SM5170 Data sheet ( Hoja de datos )
| Número de pieza | SM5170 | |
| Descripción | PLL Synthesizer IC | |
| Fabricantes | Nippon Precision Circuits Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SM5170 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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NIPPON PRECISION CIRCUITS INC.
SM5170AV
PLL Synthesizer IC
OVERVIEW
The SM5170AV is a PLL synthesizer IC developed
for application in pagers. It incorporates indepen-
dently-controlled reference frequency and FIN input
frequency dividers, and operates from a low-voltage
supply to realize low power dissipation. It features a
charge pump that operates at 3 V, making possible a
wide range of VCO designs.
FEATURES
s Supply voltages
• VDD1 = 0.95 to 1.2 V
(prescaler, counters)
• VDD2 = 2.0 to 3.3 V (charge pump)
s FIN input frequency
• fFIN = 300 MHz (VDD1 = 0.95 V)
• fFIN = 330 MHz (VDD1 = 1.0 V)
s Reference frequency
• fXIN = 25 MHz (VDD1 = 0.95 V)
s 20 to 262140 reference frequency divider ratio
range (with 1/4 prescaler built-in)
s 1056 to 131071 FIN input frequency divider ratio
range
s −10 to 60 °C operating temperature range
s 16-pin VSOP
PINOUT
(Top view)
XIN
XOUT
VDD2
DB
DO
VSS
FIN
VDD1
1
8
16 TEST
NC
OPR
LE
DATA
CLK
LD
9 NC
ORDERING INFORMATION
Device
SM5170AV
Package
16-pin VSOP
NIPPON PRECISION CIRCUITS—1
1 page  
SM5170AV
FUNCTIONAL DESCRIPTION
Frequency Divider Data
The input data should be specified keeping in mind
the VDD2 supply. The data is input using CLK,
DATA and LE pins into the shift register and latch
which operate from the VDD2 supply. The VDD1 sup-
ply level, however, is not needed and can be ON or
OFF.
The control data input uses a 3-line 24-bit serial
interface comprising the clock (CLK), data input
(DATA) and latch enable (LE). The data is input with
the MSB first. The last two bits (23rd + 24th) are
used as the latch select control bits. Data is written to
the shift register on the rising edge of the clock sig-
nal. Accordingly, the data should change state on the
falling edge of the clock signal. Data is transferred
from the shift register to the latch when the latch
enable (LE) signal goes HIGH. Accordingly, the
latch enable signal should be held LOW while data is
being written to the shift register.
The clock and data input signals are both ignored
when the latch enable signal goes HIGH. Also, the
CLK, DATA and LE inputs should be tied LOW
when not setting data.
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DATA MSB
LSB
LE Control bits
Input Data Description
Latch select
Figure 1. Frequency divider data format
MSB LSB
DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Control bits
Figure 2. Latch select data format
The last two data bits determine the status of the shift register data latch.
Bit 23
0
0
Bit 24
0
1
Latch
S w allow counter and main counter frequency
divider ratio latch select
Reference frequency counter divider ratio
data and LD output latch select
FIN input frequency Divider (N-counter) Structure
The FIN input frequency divider generates a compar-
ator frequency signal (FV), which is input to the
phase comparator, by dividing the VCO signal input
on pin FIN.
The phase comparator is comprised of dual modulus
prescalers, a 5-bit swallow counter and a 12-bit main
counter.
Frequency settings
Prescaler
Swallow counter
Main counter
FIN input frequency divider ratio
Counter set ranges Prescaler
Swallow counter
Main counter
FIN input frequency divider ratio range
P and P + 1
S
M
N = (P + 1) × S + P × (M − S)
N = P × M + S (where M > S)
P = 32, P + 1 = 33
S = 0 to 31
M = 32 to 4095
N = 1056 to 131071
NIPPON PRECISION CIRCUITS—5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SM5170.PDF ] | |
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