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PDF SM5166AV Data sheet ( Hoja de datos )
| Número de pieza | SM5166AV | |
| Descripción | PLL Synthesizer IC | |
| Fabricantes | Nippon Precision Circuits Inc | |
| Logotipo |  |
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NIPPON PRECISION CIRCUITS INC.
SM5166AV
PLL Synthesizer IC
OVERVIEW
The SM5166AV is a PLL synthesizer IC developed
for application in pagers and fabricated using NPC’s
Molybdenum-gate CMOS process. It incorporates
independently-controlled reference frequency and
operating frequency dividers, and operates from a
low-voltage supply to realize low power dissipation.
It features a charge pump that operates at 3 V,
making possible a wide range of VCO designs.
FEATURES
s Operating frequency
• fFIN = 100 MHz (VDD1 = 1.00 V)
• fFIN = 90 MHz (VDD1 = 0.95 V)
s Reference frequency
• fXIN = 25 MHz
(VDD1 = 0.95 V, External Input)
• fXIN = 16 MHz*
(VDD1 = 0.95 V, Internal oscillaton)
NOTE) * : NPC’s recommended frequency.
Confirm with crystal supplier.
s Unlock signal output pin
s Output circuit for passive filter connection
s −10 to 60 °C operating temperature range
s Standby function for low current consumption
s Boost-up signal output for fast locking
s Supply voltages
• VDD1 = 0.95 to 1.5 V
(prescaler, counters)
• VDD2 = 2.0 to 3.3 V
(charge pump)
s 40 to 65528 reference frequency divider ratio
range (with 1/8 prescaler built-in) set by serial
input data
s 1056 to 65535 operating frequency divider ratio
range set by serial input data
s 16-pin VSOP
s Molybdenum-gate CMOS process
PINOUT(TOP VIEW)
XIN
XOUT
VDD2
DB
DO
VSS
FIN
VDD1
1
8
16 TEST
NC
OPR
LE
DATA
CLK
LD
9 NC
PACKAGE DIMENSIONS
Unit: mm
16-pin VSOP
5.1 0.2
0.22+-
0.10
0.05
0.65
0.15+-00..1005
0 10
0.5 0.2
NIPPON PRECISION CIRCUITS—1
1 page  
SM5166AV
FUNCTIONAL DESCRIPTION
Operating Frequency Divider
(N-counter) Structure
The operating frequency divider generates a
comparator frequency signal (FV), which is input to
the phase comparator, by dividing the VCO signal
input on pin FIN.
The operating frequency divider is comprised by
dual modulus prescalers, a 5-bit swallow counter and
a 11-bit main counter.
The settings for the prescaler (P and P + 1), swallow
counter (S) and main counter (M) are related to the
comparator frequency divider ratio by:
N = (P + 1) × S + P(M – S)
= PM + S
The counter value ranges are P = 32, P + 1 = 33, S =
0 to 31, and M = 32 to 2047. Therefore, the operating
frequency divider ratio range N is 1056 to 65535.
Reference Frequency Divider
(R-counter) Structure
The reference frequency divider generates a
comparator frequency signal (FR), which is input to
the phase comparator, by dividing the reference
frequency input either from an external signal on
XIN or from a crystal connected between XIN and
XOUT.
The reference frequency divider is comprised by a
fixed divide-by-8 prescaler and an 13-bit reference
counter.
The settings for the prescaler (A = 8) and reference
counter (R) are related to the reference frequency
divider ratio by:
R = AB = 8B
The counter value ranges are A = 8 and B = 5 to
8191. Therefore, the reference frequency divider
ratio range is R = 40 to 65528.
Input Data
The input data should be specified keeping in mind
the VDD2 supply. The data is input using CLK,
DATA and LE pins into the shift register and latch
which operate from the VDD2 supply. However, the
VDD1 supply level can vary.
The control data input uses a 3-line 17-bit serial
interface comprising the clock (CLK), data input
(DATA) and latch enable (LE). The data is input with
the MSB first. The last (17th) bit is used as the latch
select control bit. Data is written to the shift register
on the rising edge of the clock signal. Accordingly,
the data should change state on the falling edge of
the clock signal. Data is transferred from the shift
register to the latch when the latch enable (LE)
signal goes HIGH. Accordingly, the latch enable
signal should be held LOW while data is being
written to the shift register.
The clock and data input signals are both ignored
when the latch enable signal goes HIGH. Also, the
CLK, DATA and LE inputs should be tied LOW
when not setting data.
NIPPON PRECISION CIRCUITS—5
5 Page 
INPUT/OUTPUT EQUIVALENT
XIN, XOUT
SM5166AV
CIRCUITS
DO
XOUT
From
Internal
Circuit
XIN
VDD1
Internal
Circuit
VDD1
To
Internal
Counter
VDD1
From
Internal
Circuit
Transistor
Resistor
Lagging Phase
Correction Signal
Leading Phase
Correction Signal
LD
From
Internal
Circuit
VDD2
DO
VDD2
LD
FIN
From
Internal
Circuit
FIN1
VDD1
VDD1
To
Internal
Counter
OPR, CLK, DATA, LE
Diffused Resistor
OPR
CLK
DATA
LE
VDD2
To
Internal
Circuit
DB
From
Internal
Circuit
From
Internal
Circuit
VDD2
DB
TEST
VDD1
TEST
Transistor Resistor
VDD1
To
Internal
Circuit
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, 2-chome Fukuzumi
Koutou-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9610BE 1997.05
NIPPON PRECISION CIRCUITS—11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet SM5166AV.PDF ] | |
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