|
|
PDF ISL6556A Data sheet ( Hoja de datos )
| Número de pieza | ISL6556A | |
| Descripción | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL6556A (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
®
Data Sheet
March 2003
ISL6556A
FN9096.1
Optimized Multi-Phase PWM Controller
with 6-Bit DAC for VR10.X Application
The ISL6556A controls microprocessor core voltage
regulation by driving up to 4 synchronous-rectified buck
channels in parallel. Multi-phase buck converter architecture
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents. Lower ripple
results in fewer components, lower component cost,
reduced power dissipation, and smaller implementation
area.
The ISL6556A utilizes rDS(ON) current sensing in each
phase for adaptive voltage positioning (droop), channel-
current balancing, and over-current protection. To ensure
droop accuracy, an external NTC compensation circuit can
be used to completely nullify the effect of temperature
related variation in rDS(ON).
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be eliminated using the remote-sense
amplifier. The precision threshold-sensitive enable input is
available to accurately coordinate the start up of the
ISL6556A with Intersil MOSFET driver IC. Dynamic-VID™
technology allows seamless on-the-fly VID changes. The
offset pin allows accurate voltage offset settings that are
independent of VID setting. The ISL6556A uses 5V bias and
has a built-in shunt regulator to allow 12V bias using only a
small external limiting resistor.
Pinouts
32-LEAD QFN
TOP VIEW
VID3 1
VID2 2
VID1 3
VID0 4
VID12.5 5
OFS 6
DAC 7
REF 8
24 PWM4
23 ISEN4
22 ISEN2
21 PWM2
20 PWM1
19 ISEN1
18 GND
17 ISEN3
Features
• Precision Multi-Phase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Temperature and Life
- Adjustable Reference-Voltage Offset
• Precision rDS(on) Current Sensing
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Low-Cost, Lossless Current Sensing
• Internal Shunt Regulator for 5V or 12V Biasing
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
• Threshold Enable Function for Precision Sequencing
• Over Current Protection
• Over-Voltage Protection
- No Additional External Components Needed
- OVP Pin to drive optional Crowbar Device
• 2, 3, or 4 Phase Operation up to 1.5MHz per Phase
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6556ACB
0 to 105 28-PIN SOIC
ISL6556ACR
0 to 105 32-PIN QFN
PKG. NO.
M28.3
L32.5X5B
28-PIN SOIC
TOP VIEW
OVP 1
PGOOD 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
VID12.5 8
OFS 9
DAC 10
REF 11
FB 12
COMP 13
VDIFF 14
28 FS
27 EN
26 VCC
25 PWM4
24 ISEN4
23 ISEN2
22 PWM2
21 PWM1
20 ISEN1
19 ISEN3
18 PWM3
17 GND
16 RGND
15 VSEN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Dynamic VID™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Application of ISL6556ACR
ISL6556A
+12V
+5V
FB
VDIFF
VSEN
RGND
COMP VCC
EN
DAC
PGOOD
REF
OVP
OFSOUT
ISL6556ACR
VID4
VID3
VID2
ISEN1
PWM1
PWM2
VID1
ISEN2
VID0
VID12.5
PWM3
ISEN3
OFS
FS
GND ENLL
RT
PWM4
ISEN4
EN
VID_PGOOD
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
+12V
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
+12V
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
+12V
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
5
VIN
NTC
THERMISTOR
VIN
VIN
µP
LOAD
VIN
5 Page 
ISL6556A
sample currents are summed and divided by the number of
active channels. The resulting average current, IAVG,
provides a measure of the total load current demand on the
converter and the appropriate level of channel current. Using
Figures 3 and 4, the average current is defined as
IAVG
=
I--1-----+-----I--2----+-----…--------+-----I--N--
N
(EQ. 4)
IAVG
=
I--O-----U----T--
N
-r--D----S----(--O----N-----)
RISEN
where N is the number of active channels and IOUT is the
total load current.
VCOMP
+
-
+
PWM1
-
f(jω)
SAWTOOTH SIGNAL
IER
IAVG
-
÷N
+
Σ
I4 *
I3 *
I2
I1
NOTE: *Channels 3 and 4 are optional.
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
The average current is subtracted from the individual
channel sample currents. The resulting error current, IER, is
filtered to modify VCOMP. The modified VCOMP signal is
compared to a sawtooth ramp signal to produce a modified
pulse width which corrects for any unbalance and drives the
error current toward zero. Figure 4 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided,
resulting in a cost-effective and easy-to-implement solution
relative to single-phase conversion. Channel-current
balance insures that the thermal advantage of multi-phase
conversion is realized. Heat dissipation in multiple channels
is spread over a greater area than can easily be
accomplished using the single phase approach.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able
to cool more effectively than the other(s) due to nearby air
flow or heat sinking components. The other channel(s) may
have more difficulty cooling with comparatively less air flow
and heat sinking. The hotter channels may also be located
close to other heat-generating components tending to drive
their temperature even higher. In these cases, the proper
selection of the current sense resistors (RISEN in Figure 3)
introduces channel current unbalance into the system.
Increasing the value of RISEN in the cooler channels and
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
Voltage Regulation
The integrating compensation network shown in Figure 5
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6556A to include the
combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 5.
EXTERNAL CIRCUIT
RC CC COMP
ISL6556A INTERNAL CIRCUIT
RREF
CREF
DAC
REF
RFB
+
VDROOP
-
FB
VDIFF
+
- VCOMP
ERROR AMPLIFIER
IAVG
VOUT+
VOUT-
VSEN
RGND
+
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADUJUSTMENT
The ISL6556A incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the non-
inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ISL6556A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL6556A | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application | Intersil Corporation |
| ISL6556B | Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |