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PDF ISL6551 Data sheet ( Hoja de datos )
| Número de pieza | ISL6551 | |
| Descripción | ZVS Full Bridge PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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DATASHEET
ZVS Full Bridge PWM Controller
ISL6551
The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM
controller designed for isolated power systems. This part
implements a unique control algorithm for fixed-frequency ZVS
current mode control, yielding high efficiency with low EMI. The
two lower drivers are PWM controlled on the trailing edge and
employ resonant delay while the two upper drivers are driven
at a fixed 50% duty cycle.
This IC integrates many features in 28 Ld SOIC package to
yield a complete and sophisticated power supply solution.
Control features include programmable soft-start for
controlled start-up, programmable resonant delay for zero
voltage switching, programmable leading edge blanking to
prevent false triggering of the PWM comparator due to the
leading edge spike of the current ramp, adjustable ramp for
slope compensation, drive signals for implementing
synchronous rectification in high output current, ultra high
efficiency applications and current share support for
paralleling up to 10 units, which helps achieve higher reliability
and availability as well as better thermal management.
Protective features include adjustable cycle-by-cycle peak
current limiting for overcurrent protection, fast short-circuit
protection (in hiccup mode), a latching shutdown input to turn
off the IC completely on output overvoltage conditions or other
extreme and undesirable faults, a non-latching enable input to
accept an enable command when monitoring the input voltage
and thermal condition of a converter and VDD undervoltage
lockout with hysteresis. Additionally, the ISL6551 includes
high current high-side and low-side totem-pole drivers to avoid
additional external drivers for moderate gate capacitance (up
to 1.6nF at 1MHz) applications, an uncommitted high
bandwidth (10MHz) error amplifier for feedback loop
compensation, a precision bandgap reference with ±1.5%
(ISL6551AB) or ±1% (ISL6551IB) tolerance across
recommended operating conditions and a ±5% “in regulation”
monitor.
In addition to the ISL6551, other external elements such as
transformers, pulse transformers, capacitors, inductors and
Schottky or synchronous rectifiers are required for a complete
power supply solution. A detailed 200W telecom power supply
reference design using the ISL6551 with companion Intersil
ICs, Supervisor and Monitor ISL6550, and Half-bridge Driver
HIP2100, is presented in application note AN1002.
In addition, the ISL6551 can also be designed in push-pull
converters using all of the features except the two upper
drivers and adjustable resonant delay features.
Features
• High speed PWM (up to 1MHz) for ZVS full bridge control
• Current mode control compatible
• High current high-side and low-side totem-pole drivers
• Adjustable resonant delay for ZVS
• 10MHz error amplifier bandwidth
• Programmable soft-start
• Precision bandgap reference
• Latching shutdown input
• Non-latching enable input
• Adjustable leading edge blanking
• Adjustable dead time control
• Adjustable ramp for slope compensation
• Fast short-circuit protection (hiccup mode)
• Adjustable cycle-by-cycle peak current limiting
• Drive signals to implement synchronous rectification
• VDD undervoltage lockout
• Current share support
• ±5% “in regulation” indication
• Pb-free (RoHS compliant)
Applications
• Full-bridge and push-pull converters
• Power supplies for off-line and Telecom/Datacom
• Power supplies for high end microprocessors and servers
Related Literature
• AN1002, 200W, 470kHz, Telecom Power Supply Using
ISL6551 Full-Bridge Controller and ISL6550 Supervisor and
Monitor.
April 30, 2015
FN9066.6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003-2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Functional Block Diagram
ISL6551
BANDGAP
REFERENCE
BGREF 8
PKILIM 7
R_LEB 9
R_RESDLY 4
RESODLY
ISENSE 6
R_RA 5
CT 2
RD 3
EAO 14
RAMP
ADJUST
CLOCK
GENERATOR
ERROR AMP
Figure 7
EAI 13
EANI 12
DC OK
UVLO
SSHHUUTTDDOOWWNN
LLAATTCCHH
SSOOFFT-T
SSTTAARRTT
SSHHUUTTDDOOWWNN
UPPER1
DRIVER
27 VDDP1
24 UPPER1
LEB
PWM
LOGIC
UPPER2
DRIVER
23 UPPER2
LOWER1
DRIVER
26 VDDP2
22 LOWER1
CURRENT
SHARE
LOWER2
DRIVER
21 LOWER2
CIRCUITS REFERENCED TO VSS
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5
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FN9066.6
April 30, 2015
5 Page 
ISL6551
Block/Pin Functional
Descriptions
Detailed descriptions of each individual block in the functional
block diagram on page 5 are included in this section.
Application information and design considerations for each pin
and/or each block are also included.
• IC Bias Power (VDD, VDDP1, VDDP2)
- The IC is powered from a 12V ±10% supply.
- VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
- VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
- Heavy copper should be attached to these pins for a
better heat spreading.
• IC GNDs (VSS, PGND)
- VSS is the reference ground, the return of VDD, of all
control circuits and must be kept away from nodes with
switching noises. It should be connected to the PGND in
only one location as close to the IC as practical. For a
secondary side control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinout(s). For a primary side control system, it should be
connected to the net before the input capacitors, i.e., the
input return pinout(s).
- PGND is the power return, the high-current return path of
both VDDP1 and VDDP2. It should be connected to the
SOURCE pins of two lower power switches or the RETURNs
- of external drivers as close as possible with heavy copper
traces.
- Copper planes should be attached to both pins.
• Undervoltage Lockout (UVLO)
- UVLO establishes an orderly start-up and verifies that VDD
is above the turn-on threshold voltage (VDDON). All the
drivers are held low during the lockout. UVLO incorporates
hysteresis VDDHYS to prevent multiple startup/shutdowns
while powering up.
- UVLO limits are not applicable to VDDP1 and VDDP2.
• Bandgap Reference (BGREF)
- The reference voltage VREF is generated by a precision
bandgap circuit.
- This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
- This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
• Clock Generator (CT, RD)
- This free-running oscillator is set by two external
components as shown in Figure 4. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD
and CT should be tied to the VSS pin on their other ends
as close as possible. The corresponding CT for a particular
frequency can be selected from Figure 5.
- The switching frequency (fsw) of the power train is half of
the clock frequency (Fclock), as shown in Equation 1.
fsw = F-----c---l-2-o----c---k--
(EQ. 1)
RD
SET CLOCK
DEAD TIME (DT)
RD
VDD-
I_CT
VMAX
- OUT
+
CLK
CT S Q
Q
CT
VMIN
- OUT
+
RQ
Q
I_CT
CLK
DT
DT
FIGURE 4. SIMPLIFIED CLOCK GENERATOR CIRCUIT
Submit Document Feedback 11
FN9066.6
April 30, 2015
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL6551.PDF ] | |
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