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PDF ISL6151 Data sheet ( Hoja de datos )
| Número de pieza | ISL6151 | |
| Descripción | Negative Voltage Hot Plug Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6141, ISL6151
May 2002
FN9079
Negative Voltage Hot Plug Controller
The ISL6141 is an 8-pin, negative voltage hot plug controller
that allows a board to be safely inserted and removed from a
live backplane. Inrush current is limited to a programmable
value by controlling the gate voltage of an external N-
channel pass transistor. The pass transistor is turned off if
the input voltage is less than the Under-Voltage threshold, or
greater than the Over-Voltage threshold. The IntelliTripTM
electronic circuit breaker and programmable current limit
features protect the system against short circuits. When the
Over-Current threshold is exceeded, the output current is
limited for 600µs before the circuit breaker shuts down the
FET. If the fault disappears before the 600µs time-out,
normal operation resumes. In addition, the IntelliTripTM
electronic circuit breaker has a fast Hard Fault shutdown
with a threshold set at 4 times the current limit value. When
activated, the GATE is immediately turned off and then
slowly turned back on for a single retry (soft-start). The
active low PWRGD signal can be used to directly enable a
power module (with a low enable input). The ISL6151 is the
same device but has an active high PWRGD output.
Ordering Information
PART NO. TEMP. RANGE (oC) PACKAGE PKG. NO.
ISL6141CB
0 to 70
8 Lead SOIC M8.15
ISL6151CB
0 to 70
8 Lead SOIC M8.15
ISL6141IB
-40 to 85
8 Lead SOIC M8.15
ISL6151IB
-40 to 85
8 Lead SOIC M8.15
Typical Application (RL, CL are the Load)
GND
GND
R4
UV
VDD
R5 ISL6141
OV
R6 VEE SENSE GATE
PWRGD
DRAIN
(LOAD)
-48V IN
R1
R1 = 0.02Ω (1%)
C1
R3
R2
C2
Q1
C1 = 150nF (25V)
CL
RL
-48V OUT
R2 = 10Ω (5%)
C2 = 3.3nF (100V)
R3 = 18kΩ (5%)
Q1 = IRF530 (100V, 17A, 0.11Ω)
R4 = 549kΩ (1%)
CL = 100µF (100V)
R5 = 6.49kΩ (1%)
RL = equivalent load
R6 = 10kΩ (1%)
Features
• Operates from -20V to -80V (-100V Absolute Max Rating)
• Programmable Inrush Current
• Programmable Over-Voltage Protection
• Programmable Under-Voltage Protection
- 135mV of hysteresis
- Equals ~4.6V of hysteresis at the power supply
• UVLO (Under-Voltage Lock-Out) ~ 16.5V
• Programmable Current Limit with 600µs time-out
• IntelliTripTM electronic circuit breaker distinguishes
between Over-Current and Hard Fault conditions
- Fast shutdown for Hard Faults with a single retry (fault
current > 4X current limit value).
• Pin Compatible with ISL6140/50.
• Power Good Control Output
- Monitors both the DRAIN (voltage drop across the FET)
and the GATE voltage; once both are OK, the Power
Good output is latched in the active state.
- PWRGD active high: ISL6151 (H version)
- PWRGD active low: ISL6141 (L version)
Applications
• VoIP (Voice over Internet Protocol) Servers
• Telecom systems at -48V
• Negative Power Supply Control
• +24V Wireless Base Station Power
Related Literature
• ISL6140/41 EVAL1 Board Set, Document # AN9967
• ISL6142/52 EVAL1 Board Set, Document # AN1000
• ISL6140/50 Hot Plug Controller, Document # FN9039
• ISL6116 Hot Plug Controller, Document # FN4778
NOTE: See www.intersil.com/hotplug for more information.
Pinout
ISL6141 OR ISL6151 (8 LEAD SOIC)
PWRGD/PWRGD 1
OV 2
UV 3
VEE 4
TOP VIEW
8 VDD
7 DRAIN
6 GATE
5 SENSE
ISL6141 has active low (L version) PWRGD output pin
ISL6151 has active high (H version) PWRGD output pin
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Intellitrip™ is a trademark of Intersil Americas Inc.
1 page  
ISL6141, ISL6151
Electrical Specifications
CVoDmDm=e+rc4i8aVl (,0VoECEto=
+0V Unless Otherwise Specified. All tests are over the full temperature range;
70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC. (Continued)
either
PARAMETER
SYMBOL
TEST CONDITIONS
UV Pin Input Current
OV pin
IINUV
VUV = VEE
OV Pin High Threshold Voltage
OV Pin Low Threshold Voltage
OV Pin Hysteresis
OV Pin Input Current
DRAIN Pin
VOVH
VOVL
VOVHY
IINOV
OV Low to High Transition
OV High to Low Transition
VOV = VEE
Power Good Threshold (PWRGD/PWRGD
active)
VPG
VDRAIN - VEE
DRAIN Input Bias Current
ISL6141 (PWRGD Pin: L Version)
IDRAIN VDRAIN = 48V
PWRGD Output Low Voltage
Output Leakage
ISL6151 (PWRGD Pin: H Version)
VOL1
VOL5
IOH
(VDRAIN - VEE) < VPG; IOUT = 1mA
(VDRAIN - VEE) < VPG; IOUT = 5mA
VDRAIN = 48V, V PWRGD = 80V
PWRGD Output Low Voltage (PWRGD-DRAIN)
PWRGD Output Impedance
AC Timing
VOL
ROUT
VDRAIN = 5V, IOUT = 1mA
(VDRAIN - VEE) < VPG
OV High to GATE Low
OV Low to GATE High
UV Low to GATE Low
UV High to GATE High
SENSE High to GATE Low
Current Limit to GATE Low (O.C. Time-out)
Hard Fault to GATE Low (200mV comparator)
Typical GATE shutdown based on application
ckt. Guaranteed by design.
tPHLOV Figures 2A, 3A
tPLHOV Figures 2A, 3A
tPHLUV Figures 2A, 3B
tPLHUV Figures 2A, 3B
tPHLSENSE Figures 2A, 6
tPHLCB Figures 2B, 8
tPHLHF Figures 7, 23, 27 (zero Ω short to VDD)
ISL6141 (L Version)
DRAIN Low to PWRGD Low
GATE High to PWRGD Low
ISL6151 (H Version)
tPHLDL
tPHLGH
Figures 2A, 4A (note 2)
Figures 2A, 5A (note 2)
DRAIN Low to (PWRGD-DRAIN) High
GATE High to (PWRGD-DRAIN) High
tPLHDL
tPLHGH
Figures 2A, 4B (note 2)
Figures 2A, 5B (note 2)
MIN TYP MAX Units
-0.05 -0.5 µA
1.235 1.255 1.275
1.215 1.230 1.255
25
-0.05 -0.5
V
V
mV
µA
0.80 1.30 2.00
V
38 60 µA
- 0.30 1.0 V
- 1.50 3.0 V
- 0.05 10 µA
- 0.85 1.0
3.5 6.2 9.0
V
kΩ
0.6 1.3 3.0 µs
1.0 4.5 12.0 µs
0.6 0.90 3.0
µs
1.0 5.0 12.0 µs
0.35 3
µs
600 µs
10 µs
3.0 5.0 µs
1.0 3.0 µs
3.0 5.0 µs
0.4 3.0 µs
5
5 Page 
ISL6141, ISL6151
R1 - Is the Over-Current sense resistor. If the input current is
high enough, such that the voltage drop across R1 exceeds
the SENSE comparator trip point (50mV nominal), the GATE
pin will be pulled lower (to ~4V) and current will be regulated
to 50mV/Rsense for approximately 600µs. The Over-Current
threshold is defined in Equation 3 below. If the 600µs time-
out period is exceeded the Over-Current latch will be set and
the FET will be turned off to protect the load from excessive
current. A typical value for R1 is 0.02Ω, which sets an Over-
Current trip point of; IOC = V/R = 0.05/0.02 = 2.5 Amps. To
select the appropriate value for R1, the user must first
determine at what level of current it should trip, take into
account worst case variations for the trip point (50mV
±10mV = ±20%), and the tolerances of the resistor (typically
1% or 5%). Note that the Over-Current threshold should be
set above the inrush current level plus the expected load
current to avoid activating the current limit and time-out
circuitry during start-up. If the power good output is used to
enable an external module, the desired inrush current only
needs to be considered. One rule of thumb is to set the
Over-Current threshold 2-3 times higher than the normal
operating current.
IOC = R---5--s-0--e--m-n----sv---e-
(EQ. 3)
Physical layout of R1 SENSE resistor is critical to avoid
the possibility of false over current events. Since it is in the
main input-to-output path, the traces should be wide enough
to support both the normal current, and up to the over-
current trip point. Ideally trace routing between the R1
resistor and the ISL6141/51 (pin 4 (VEE) and pin 5 (SENSE)
is direct and as short as possible with zero current in the
sense lines. (See Figure 24).
CORRECT
INCORRECT
To SENSE
and VEE
CURRENT
SENSE RESISTOR
FIGURE 24. SENSE RESISTOR LAYOUT GUIDELINES
CL - is the sum of all load capacitances, including the load’s
input capacitance itself. Its value is usually determined by
the needs of the load circuitry, and not the hot plug (although
there can be interaction). For example, if the load is a
regulator, then the capacitance may be chosen based on the
input requirements of that circuit (holding regulation under
current spikes or loading, filtering noise, etc.) The value
chosen will affect the peak inrush current. Note that in the
case of a regulator, there may be capacitors on the output of
that circuit as well; these need to be added into the
capacitance calculation during inrush (unless the regulator is
delayed from operation by the PWRGD signal).
RL - is the equivalent resistive value of the load and
determines the normal operation current delivered through
the FET. It also affects some dynamic conditions (such as
the discharge time of the load capacitors during a power-
down). A typical value might be 48Ω (I = V/R = 48/48 = 1A).
R2, C1, R3, C2 - are related to the GATE driver, as it
controls the inrush current.
R2 prevents high frequency oscillations; 10Ω is a typical
value. R2 = 10Ω.
R3 and C2 act as a feedback network to control the inrush
current as shown in equation 4 below, where CL is the load
capacitance (including module input capacitance), and IPU is
the GATE pin charging current, nominally 50µA.
Iinrush = IPU × CC-----L2-
(EQ. 4)
Begin by choosing a value of acceptable inrush current for
the system, and then solve for C2.
C1 and R3 prevent Q1 from turning on momentarily when
power is first applied. Without them, C2 would pull the gate
of Q1 up to a voltage roughly equal to VEE*C2/Cgs(Q1)
(where Cgs is the FET gate-source capacitance) before the
ISL6141/2 could power up and actively pull the gate low.
Place C1 in parallel with the gate capacitance of Q1; isolate
them from C2 by R3.
C1= [(Vinmax - Vth)/Vth] * (C2+Cgd) - where Vth is the
FET’s minimum gate threshold, Vinmax is the maximum
operating input voltage, and Cgd is the FET gate-drain
capacitance.
R3 - its value is not critical, a typical value of 18kΩ is
recommended but values down to 1KΩ can be used. Lower
values of R3 will add delay to the gate turn-on for hot
insertion and the single retry event following a hard fault.
Note that although this IC was designed for -48V systems, it
can also be used as a low-side switch for positive 48V
systems; the operation and components are usually similar.
One possible difference is the kind of level shifting that may
be needed to interface logic signals to the UV input (to reset
the latch) or PWRGD output. For example, many of the IC
functions are referenced to the IC substrate, connected to
the VEE pin. But this pin may be considered -48V or GND,
depending upon the polarity of the system. And input or
output logic (running at 5V or 3.3V or even lower) might be
externally referenced to either VDD or VEE of the IC, instead
of GND.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL6151.PDF ] | |
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