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PDF IXDD404 Data sheet ( Hoja de datos )
| Número de pieza | IXDD404 | |
| Descripción | 4 Amp Dual Low-Side Ultrafast MOSFET Driver | |
| Fabricantes | IXYS Corporation | |
| Logotipo |  |
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IXDD404
4 Amp Dual Low-Side Ultrafast MOSFET Driver
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected
• High Peak Output Current: 4A Peak
• Wide Operating Range: 4.5V to 35V
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two identical drivers in single chip
Applications
• Driving MOSFETs and IGBTs
• Limiting di/dt under Short Circuit
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Class D Switching Amplifiers
General Description
The IXDD404 is comprised of two 4 Amp CMOS high speed
MOSFET drivers. Each output can source and sink 4 A of
peak current while producing voltage rise and fall times of less
than 15ns to drive the latest IXYS MOSFETS & IGBT's. The
input of the driver is compatible with TTL or CMOS and is fully
immune to latch up over the entire operating range. Designed
with small internal delays, cross conduction/current shoot-
through is virtually eliminated in the IXDD404. Improved speed
and drive capabilities are further enhanced by very low,
matched rise and fall times.
Additionally, each driver in the IXDD404 incorporates a unique
ability to disable the output under fault conditions. When a
logical low is forced into the Enable input of a driver, both of it's
final output stage MOSFETs (NMOS and PMOS) are turned
off. As a result, the respective output of the IXDD404 enters a
tristate mode and achieves a Soft Turn-Off of the MOSFET/
IGBT when a short circuit is detected. This helps prevent
damage that could occur to the MOSFET/IGBT if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
The IXDD404 is available in the standard 8 pin P-DIP (PI),
SOIC-8 (SIA) and SOIC-16 (SIA-16) packages. For enhanced
thermal performance, the SOP-8 and SOP-16 are also avail-
able with an exposed grounded metal back package as the SI
and SI-16 respectively.
Ordering Information
Part Number
Package Type
Temp. Range
IXDD404PI
8-Pin PDIP
IXDD404SI
IXDD404SIA
IXDD404SI-16
8-Pin SOIC with Grounded Metal Back
8-Pin SOIC
16-Pin SOIC with Grounded Metal Back
-55°C to
+125°C
IXDD404SIA-16 16-Pin SOIC
NOTE: Mounting or solder tabs on all packages are connected to ground
Configuration
Dual Non
Inverting With
Enable
Figure 1 - Functional Diagram
Vcc
ENA
200k
OUTA
INB
ENB
GND
Copyright © IXYS CORPORATION 2004
200k
OUTB
First Release
DS99046D(11/10)
1 page  
Fig. 3
80
70
60
50
40
30
20
10
0
5
Typical Performance Characteristics
IXDD404
Rise Times vs. Supply Voltage
10 15 20 25 30
Supply Voltage (V)
10000pF
6800pF
4700pF
1800pF
1000pF
200pF
35
Fig. 4
80
70
60
50
40
30
20
10
0
5
Fall Times vs. Supply Voltage
10 15 20 25 30
Supply Voltage (V)
10000pF
6800pF
4700pF
1800pF
1000pF
200pF
35
Fig. 5
80
70
60
50
40
30
20
10
0
0
Rise Times vs. Load Capacitance
8V
10V
12V
18V
25V
35V
2000
4000
6000
8000
Load Capacitance (pF)
10000
Fig. 6
80
70
60
50
40
30
20
10
0
0
Fall Times vs. Load Capacitance
8V
10V
12V
18V
25V
35V
2000
4000
6000
8000
Load Capacitance (pF)
10000
Fig. 7
14
Rise And Fall Times vs. Temperature
CL = 1000pF, Vcc = 18V
12
tR
10
tF
8
6
4
2
0
-60
-10
40
90 140 190
Temperature (C)
5
Fig. 8
2.5
Max / Min Input vs. Temperature
CL = 1000pF, Vcc = 18V
2.4
2.3
2.2
Min Input High
2.1
2
Max Input Low
1.9
1.8
1.7
1.6
1.5
-60
-10 40
90 140
Temperature (C)
190
5 Page 
Supply Bypassing and Grounding Practices,
Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD404, it is very important to keep certain design
criteria in mind, in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXDD404 to charge a 2500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=2500pF &
∆t=25ns we can determine that to charge 2500pF to 25 volts in
25ns will take a constant current of 2.5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
4A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD404
must be able to draw this 2.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD404
to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXDD404
must be able to drain this 2.5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD404
and it’s load. Path #2 is between the IXDD404 and it’s power
supply. Path #3 is between the IXDD404 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD404.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the
load.
IXDD404
TTL to High Voltage CMOS Level Translation
The enable (EN) input to the IXDD404 is a high voltage
CMOS logic level input where the EN input threshold is ½
VCC, and may not be compatible with 5V CMOS or TTL input
levels. The IXDD404 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, VCC =15V
and the EN input threshold at 7.5V, a 5V CMOS logical high
input applied to this typical IXDD404 application’s EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.
The circuit in Figure 28 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD404 EN input. From the figure, VCC is the gate driver
power supply, typically set between 8V to 20V, and VDD is the
logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so that
the Q1 base is positioned at the midpoint of the expected
TTL logic transition levels.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied
to the Q1 emitter will drive it on. This causes the level
translator output, the Q1 collector output to settle to VCESATQ1
+ VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V
for VCC =15V given in the IXDD404 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 28 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage
CMOS logical EN output applied to the IXDD404 EN input
will enable it, allowing the gate driver to fully function as a
±4 Amp output driver.
The total component cost of the circuit in Figure 28 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 30 - TTL to High Voltage CMOS Level Translator
CC
(From Gate Driver
Power Supply)
10K
VDD
(From Logic
Power Supply)
3.3K R1
3.3K R2
R3
Q1
2N3904
High Voltage
CMOSEN
Output
(To IXDD404
EN Input)
or TTLInput)
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet IXDD404.PDF ] | |
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