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PDF ITF87052SVT Data sheet ( Hoja de datos )
| Número de pieza | ITF87052SVT | |
| Descripción | 3A/ 20V/ 0.115 Ohm/ P-Channel/ 2.5V Specified Power MOSFET | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
ITF87052SVT
March 2000 File Number 4800.3
3A, 20V, 0.115 Ohm, P-Channel,
2.5V Specified Power MOSFET
Packaging
TSOP-6
1
2
3
4
Symbol
DRAIN(1)
DRAIN(2)
GATE(3)
DRAIN(6)
DRAIN(5)
SOURCE(4)
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.115Ω, VGS = −4.5V
- rDS(ON) = 0.120Ω, VGS = −4.0V
- rDS(ON) = 0.190Ω, VGS = −2.5V
• 2.5 V Gate Drive Capability
• Small Profile Package
• Gate to Source Protection Diode
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
• Switching Time vs RGS Curves
Ordering Information
PART NUMBER
PACKAGE
BRAND
ITF87052SVT
TSOP-6 (SC-95) 052
NOTE: When ordering, use the entire part number. ITF87052SVT is
available only in tape and reel.
Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified
ITF87052SVT
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = -4.5V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 25oC, VGS = -4.0V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous
Continuous
(TA=
(TA=
100oC,
100oC,
VGS
VGS
=
=
-4.0V)
-2.5V)
(Note
(Note
2) .
2) .
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ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Power Dissipation (Note 2)
Derate Above 25oC . . . .
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PD
...
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
1. TJ = 25oC to 125oC.
2. 62.5oC/W measured using FR-4 board with 0.40 in2 (258.1 mm2) copper pad at 2 second.
-20
-20
−12/+6
3.0
3.0
1.5
1.5
Figure 4
2.0
16
-55 to 150
300
260
V
V
V
A
A
A
A
W
mW/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
SABER© is a Copyright of Analogy Inc. PSPICE® is a registered trademark of MicroSim Corporation.
www.intersil.com or 321-724-7143 | Copyright © Intersil Corporation 2000
1 page  
ITF87052SVT
Typical Performance Curves (Continued)
1.10
ID = -250µA
1.05
1000
1.00
CISS = CGS + CGD
COSS ≅ CDS + CGD
0.95
0.90
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
-5
VDD = -10V
-4
-3
-2
-1
0
0
WAVEFORMS IN
DESCENDING ORDER:
ID = -3A
ID = -1.5A
246
Qg, GATE CHARGE (nC)
8
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
VGS = 0V, f = 1MHz
CRSS = CGD
100
-0.1
-1
-10
VDS, DRAIN TO SOURCE VOLTAGE (V)
-20
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
1500
1200
VGS = -2.5V, VDD = -10V, ID = -1.5A
900
tr
tf
600 td(OFF)
300 td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
1250
VGS = -4.5V, VDD = -10V, ID = -3A
1000
750
500
td(OFF)
tf
tr
250 td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
5 Page 
ITF87052SVT
MO-193AA (TSOP-6)
6 LEAD JEDEC MO-193AA TSOP PLASTIC PACKAGE
(SIMILAR TO SSOT™-6)
A
E
E1
A
1
e
D
b
C
L
0.039
1.00
0.024
0.60
0o-8o
0.004in
0.10mm
0.037
0.95
0.075
1.90
0.095
2.40
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.035
0.043
0.90
1.10
A1 0.004
0.10
b
0.012
0.020
0.30
0.50
c
0.003
0.008
0.08
0.20
D
0.107
0.122
2.70
3.10
2
E
0.103
0.118
2.60
3.00
E1
0.056
0.070
1.40
1.80
e 0.037 BSC
0.95 BSC
3
L
0.014
0.021
0.35
0.55
4
NOTES:
1. All dimensions are within the allowable dimensions of Rev. B of
JEDEC MO-193AA outline dated 10-99.
2. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension "E " does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.006 inches
(0.15mm) per side.
4. "L" is the length of terminal for soldering.
5. Controlling dimension: Millimeter.
6. Revision 1 dated 2-00.
MO-193AA (TSOP-6)
8mm TAPE AND REEL
USER DIRECTION OF FEED
1.5mm DIAMETER HOLE
8.0mm
4.0mm
2.0mm
3.5mm
1.75mm
CL
COVER TAPE
4.0mm
17.0mm
13.0mm
178mm
13.0mm
60mm
GENERAL INFORMATION
1. 3000 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
SSOT™-6 is a trademark of Fairchild Semiconductor.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ITF87052SVT.PDF ] | |
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