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PDF ISL6721 Data sheet ( Hoja de datos )
| Número de pieza | ISL6721 | |
| Descripción | Flexible Single Ended Current Mode PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
August 2003
ISL6721
FN9110.1
Flexible Single Ended Current Mode PWM
Controller
The ISL6721 is a low power, single-ended pulse width
modulating (PWM) current mode controller designed for a
wide range of DC-DC conversion applications including
boost, flyback, and isolated output configurations. Peak
current mode control effectively handles power transients
and provides inherent over-current protection. Other
features include a low power mode where the supply current
drops to less than 200µA during over voltage and over
current shutdown faults.
This advanced BiCMOS design features low operating
current, adjustable operating frequency up to 1MHz,
adjustable soft-start, and a bi-directional SYNC signal that
allows the oscillator to be locked to an external clock for
noise sensitive applications.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG.
DWG. #
ISL6721AB
-40 to 105 16 Ld SOIC M16.15
ISL6721AV
-40 to 105 16 Ld TSSOP M16.173
Features
• 1A MOSFET Gate Driver
• 100µA Startup Current
• Fast Transient Response with Peak Current Mode Control
• Adjustable Switching Frequency up to 1MHz
• Bi-Directional Synchronization
• Low Power Disable Mode
• Delayed Restart from OV and OC Shutdown Faults
• Adjustable Slope Compensation
• Adjustable Soft Start
• Adjustable Over Current Shutdown Delay
• Adjustable UV and OV Monitors
• Leading Edge Blanking
• Integrated Thermal Shutdown
• 1% Tolerance voltage Reference
Applications
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
• Isolated Buck and Flyback Regulators
• Boost Regulators
Pinout
ISL6721 (SOIC, TSSOP)
TOP VIEW
GATE 1
ISENSE 2
SYNC 3
SLOPE 4
UV 5
OV 6
RTCT 7
ISET 8
16 VC
15 PGND
14 VCC
13 VREF
12 LGND
11 SS
10 COMP
9 FB
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6721
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic.
are at TA =
92V5o<CVC(CCo=nVtinCu<ed20) V
±10%,
Rt
=
11kΩ,
Ct
=
330
pF,
TA
=
-40
to
105oC
(Note
3),
Typical
values
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 5)
60 90 - dB
Gain-Bandwidth Product
Reference Voltage Initial Accuracy
Reference Voltage
COMP to PWM Gain, ACOMP
COMP to PWM Offset
(Note 5)
VFB = COMP, TA = 25oC (Note 5)
VFB = COMP
COMP = 4V, TA = 25oC
COMP = 4V (Note 5)
-
2.465
2.44
0.31
0.51
15
2.515
2.515
0.33
0.75
-
2.565
2.590
0.35
0.88
MHz
V
V
V/V
V
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
COMP VOL
PSRR
VFB = 0V
COMP = 1.5V, VFB = 2.7V
COMP = 1.5V, VFB = 2.3V
VFB = 2.3V
VFB = 2.7V
Frequency = 120Hz (Note 5)
-2 0.1 2 µA
2 6 - mA
-0.2 -0.5 - mA
4.25 4.4
5.0
V
0.4 0.8 1.2
V
60 80 - dB
SS Clamp, VCOMP
OSCILLATOR
SS = 2.5V, VFB = 0V, ISET = 2V
2.4
2.5
2.6
V
Frequency Accuracy
Frequency Variation with VCC
Temperature Stability
T = 105oC (F20V- - F9V)/F9V
T = -40oC (F20V- - F9V)/F9V
(Note 5)
289 318 347 kHz
- 2 3%
23
- 8 -%
Minimum Charge and Discharge Time
(Note 5)
- TBD -
nS
Maximum Duty Cycle
(Note 6)
68 75 81 %
Comparator High Threshold - Free Running
(Note 5)
-3-V
Comparator High Threshold - with External SYNCH (Note 5)
-4-V
Comparator Low Threshold
Discharge Current
(Note 5)
0 - 105oC
-40 - 105oC
- 1.5 -
V
0.75 1.0 1.2 mA
0.70 1.0
1.2
SYNCHRONIZATION
Input High Threshold
- - 2.5 V
Input Pulse Width
25 -
- nS
Input Frequency Range
(Note 5)
0.65x Free
Running
-
1.0 MHz
Input Impedance
- 4.5 - kΩ
VOH
VOL
SYNCH Advance
Output Pulse Width
RLOAD = 4.5kΩ
2.5 - - V
RLOAD = open
- - 0.1 V
SYNCH rising edge to GATE falling
edge, CGATE = CSYNCH = 100pF
-
25 55 nS
CSYNCH = 100pF
50 -
- nS
5
5 Page 
ISL6721
condition clears and the soft start voltage is below the reset
threshold, a soft start cycle begins.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the logic ground (LGND) and
connected at a single point. VC should be bypassed directly
to PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor
should be connected to the PGND ground plane.
Reference Design
The Typical Application Schematic features the ISL6721 in a
conventional dual output 10W discontinuous mode flyback
DC-DC converter. The ISL6721EVAL1 demonstration unit
implements this design and is available for evaluation.
The input voltage range is from 36 to 75V DC, and the two
outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross regulation
is achieved using the weighted sum of the two outputs.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Storage and Filtering Capacitance: C1, C2, C3
Isolation Transformer: T1
Primary voltage Clamp: CR6, R24, C18
Start Bias Regulator: R1, R2, R6, Q3, VR1
Operating Bias and Regulator: R25, Q2, D1, C5, CR2, D2
Main MOSFET Power Switch: Q1
Current Sense Network: R4, R3, R23, C4
Feedback Network:, R13, R15, R16, R17, R18, R19, R20,
R26, R27, C13, C14, U2, U3
Control Circuit:C7, C8, C9, C10, C11, C12, R5, R6, R8, R9,
R10, R11, R12, R14, R22
Output Rectification and Filtering: CR4, CR5, C15, C16,
C19, C20, C21, C22
Secondary Snubber: R21, C17
Design Criteria
The following design requirements were selected:
Switching Frequency, Fsw: 200kHz
Vin: 36 - 75V
Vout(1): 3.3V @ 2.5A
Vout(2): 1.8V @ 1.0A
Vout(bias): 12V @ 50mA
Pout: 10W
Efficiency: 70%
Maximum Duty Cycle, Dmax: 0.45
Transformer Design
The design of a flyback transformer is a non-trivial affair. It is
an iterative process which requires a great deal of
experience to achieve the desired result. It is a process of
many compromises, and even experienced designers will
produce different designs when presented with identical
requirements. The iterative design process is not presented
here for clarity.
The abbreviated design process follows:
• Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference, and
operating environment will affect the choice.
• Select suitable core material(s).
• Select maximum flux density desired for operation.
• Select core size. Core size will be dictated by the
capability of the core structure to store the required
energy, the number of turns that have to be wound, and
the wire gauge needed. Often the window area (the space
used for the windings) and power loss determine the final
core size. For flyback transformers, the ability to store
energy is the critical factor in determining the core size.
The cross sectional area of the core and the length of the
air gap in the magnetic path determine the energy storage
capability.
• Determine maximum desired flux density. Depending on
the frequency of operation, the core material selected, and
the operating environment, the allowed flux density must
be determined. The decision of what flux density to allow
is often difficult to determine initially. Usually the highest
flux density that produces an acceptable design is used,
but often the winding geometry dictates a larger core than
is required based on flux density and energy storage
calculations.
• Determine the number of primary turns.
• Determine the turns ratio.
• Select the wire gauge for each winding.
• Determine winding order and insulation requirements.
• Verify the design.
Input Power:
Pout/Efficiency = 14.3W (use 15W)
Max On Time: Ton(max) = Dmax/Fsw = 2.25µS
Average Input Current: Iavg(in) = Pin/Vin(min) = 0.42A
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL6721.PDF ] | |
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