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PDF DSP56800FM Data sheet ( Hoja de datos )
| Número de pieza | DSP56800FM | |
| Descripción | 56F801 16-bit Hybrid Controller | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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DSP56F801/D
Rev. 7.0, 1/2002
DSP56F801
Preliminary Technical Data
DSP56F801 16-bit Digital Signal Processor
• Up to 40 MIPS operation at 80 MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
• General Purpose Quad Timer
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
6
PWM Outputs
Fault Input
A/D1
4 A/D2 ADC
4 VREF
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC VDD
24
VSS
5*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Quad Timer D
Boot Flash
3
or GPIO
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2 GPIO
COP/
Watchdog
Application-
SPI Specific
4
or
GPIO
Memory &
Peripherals
••
•
PAB
•PDB
16-Bit
DSP56800
XDB2
Core
CGDB
•
XAB1
•XAB2
•INTERRUPT
IPBB
•
CONTROLS CONTROLS
16 16
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. DSP56F801 Block Diagram
GPIOB3/XTAL
GPIOB2/EXTAL
© Motorola, Inc., 2002. All rights reserved.
1 page  
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
VIL/VOL
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F801 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 through Table 13, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Power (VDD or VDDA)
Ground (VSS or VSSA)
Supply Capacitors
PLL and Clock
Interrupt and Program Control
Pulse Width Modulator (PWM) Port
Serial Peripheral Interface (SPI) Port1
Serial Communications Interface (SCI) Port1
Analog-to-Digital Converter (ADC) Port
Quad Timer Module Port
JTAG/On-Chip Emulation (OnCE)
1. Alternately, GPIO pins
Number of
Pins
5
6
2
2
2
7
4
2
9
3
6
Detailed
Description
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
MOTOROLA
DSP56F801 Preliminary Technical Data
5
5 Page 
JTAG/OnCE
2.10 JTAG/OnCE
Table 13. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
1
Signal
Name
TCK
1 TMS
1 TDI
1 TDO
1 TRST
1 DE
Signal State During
Type
Reset
Signal Description
Input
Input
Input
Output
Input
Output
Input, pulled Test Clock Input—This input pin provides a gated clock to
low internally synchronize the test logic and shift serial data to the JTAG/OnCE port.
The pin is connected internally to a pull-down resistor.
Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG
high internally TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
Input, pulled Test Data Input—This input pin provides a serial input data stream to
high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
Tri-stated
Test Data Output—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
Input, pulled Test Reset—As an input, a low signal on this pin provides a reset
high internally signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a hardware DSP
reset is required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
Output Debug Event—DE provides a low pulse on recognized debug events.
MOTOROLA
DSP56F801 Preliminary Technical Data
11
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet DSP56800FM.PDF ] | |
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