|
|
PDF DSP56002PV66 Data sheet ( Hoja de datos )
| Número de pieza | DSP56002PV66 | |
| Descripción | 24-BIT DIGITAL SIGNAL PROCESSOR | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DSP56002PV66 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
24-BIT DIGITAL SIGNAL PROCESSOR
Order this document by:
DSP56002/D, Rev. 3
DSP56002
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),
parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCE™) port. This combination of features, illustrated in Figure 1, makes the
DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital
signal processing.
1 6 3 15
16-bit Bus
24-bit Bus
24-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/O
Serial
Comm.
(SCI)
or I/O
Host
Interface
(HI)
or I/O
Program
Memory
512 × 24 RAM
64 × 24 ROM
(boot)
X Data
Memory
256 × 24 RAM
256 × 24 ROM
(A-law/ µ-law)
Y Data
Memory
256 × 24 RAM
256 × 24 ROM
(sine)
24-bit
56000 DSP
Core
Address
Generation
Unit
PAB
XAB
YAB
Internal
Data
Bus
Switch
GDB
PDB
XDB
YDB
OnCE™
Port
Clock
PLL Gen.
7
Interrupt
Control
Program
Decode
Controller
Program
Address
Generator
Program Control Unit
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
43
IRQ
Figure 1 DSP56002 Block Diagram
External
Address
Bus
Switch
Address
16
External
Data
Bus
Switch
Data
24
Bus
Control
Control
10
AA0604
©1996 MOTOROLA, INC.
1 page  
DSP56002
Product Documentation
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the
DSP56002 and are necessary to design properly with the part. Documentation is available from
one of the following locations (see back cover for detailed information):
• A local Motorola distributor
• A Motorola semiconductor sales office
• A Motorola Literature Distribution Center
• The World Wide Web (WWW)
Name
DSP56000
Family Manual
DSP56002
User’s Manual
DSP56002
Technical Data
Table 1 DSP56002 Documentation
Description
Order Number
Detailed description of the DSP56000 family
processor core and instruction set
DSP56KFAMUM/AD
Detailed functional description of the DSP56002
memory configuration, operation, and register
programming
DSP56002UM/AD
DSP56002 features list and physical, electrical, timing, DSP56002/D
and package specifications
MOTOROLA
DSP56002/D, Rev. 3
v
5 Page 
Signal/Pin Descriptions
PLL and Clock
PLL AND CLOCK
Table 1-4 PLL and Clock Signals
Signal
Name
EXTAL
XTAL
CKOUT
Signal
Type
Input
Output
Output
State
during
Reset
Signal Description
Input
Chip-
driven
Chip-
driven
External Clock/Crystal Input—This input connects the internal
oscillator input to an external crystal or to an external oscillator.
Crystal Output—This output connects the internal crystal oscillator
output to an external crystal. If an external oscillator is used, XTAL
should be left unconnected.
PLL Output Clock—When the PLL is enabled and locked, this
signal provides a 50% duty cycle output clock signal synchronized
to the internal processor clock.
When the PLL is enabled and the Multiplication Factor is less than
or equal to 4, then CKOUT is synchronized to EXTAL.
When the PLL is disabled, the output clock at CKOUT is derived
from, and has the same frequency and duty cycle as, EXTAL.
CKP
PCAP
Input
Input/
Output
Note: For information about using the PLL Multiplication Factor,
see the DSP56002 User’s Manual.
Input
PLL Output Clock Polarity Control—The value of this signal at
reset defines the polarity of the CKOUT output relative to EXTAL. If
CKP is pulled low by connecting through a resistor to ground,
CKOUT and EXTAL have the same polarity. Pulling CKP high by
connecting it through a resistor to VCC causes CKOUT and EXTAL
to be inverse polarities. The polarity of CKOUT is latched at the end
of reset; therefore, any changes to CKP after deassertion of RESET
do not affect CKOUT polarity.
Indeter-
minate
PLL Capacitor—This signal is used to connect the required external
filter capacitor to the PLL filter. Connect one end of the capacitor to
PCAP and the other to VCCP. The value of the capacitor is specified
in Section 2 of this data sheet.
MOTOROLA
DSP56002/D, Rev. 3
1-5
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DSP56002PV66.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DSP56002PV66 | 24-BIT DIGITAL SIGNAL PROCESSOR | Motorola Inc |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |