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PDF DS92LV040A Data sheet ( Hoja de datos )
| Número de pieza | DS92LV040A | |
| Descripción | 4 Channel Bus LVDS Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 2002
DS92LV040A
4 Channel Bus LVDS Transceiver
General Description
The DS92LV040A is one in a series of Bus LVDS transceiv-
ers designed specifically for high speed, low power back-
plane or cable interfaces. The device operates from a single
3.3V power supply and includes four differential line drivers
and four receivers. To minimize bus loading, the driver out-
puts and receiver inputs are internally connected. The device
also features a flow through pin out which allows easy PCB
routing for short stubs between its pins and the connector.
The driver translates 3V LVTTL levels (single-ended) to dif-
ferential Bus LVDS (BLVDS) output levels. This allows for
high speed operation while consuming minimal power and
reducing EMI. In addition, the differential signaling provides
common mode noise rejection greater than ±1V.
The receiver threshold is less than +0/−70 mV. The receiver
translates the differential Bus LVDS to standard (LVTTL/
LVCMOS) levels. (See Applications Information Section for
more details.)
Features
n Bus LVDS Signaling
n Propagation delay: Driver 2.3ns max, Receiver 3.2ns
max
n Low power CMOS design
n 100% Transition time 1ns driver typical, 1.3ns receiver
typical
n High Signaling Rate Capability (above 155 Mbps)
n 0.1V to 2.3V Common Mode Range for VID = 200mV
n 70 mV Receiver Sensitivity
n Supports open and terminated failsafe on port pins
n 3.3V operation
n Glitch free power up/down (Driver & Receiver disabled)
n Light Bus Loading (5 pF typical) per Bus LVDS load
n Designed for Double Termination Applications
n Balanced Output Impedance
n Product offered in 44 pin LLP (Leadless Leadframe
Package) package
n High impedance Bus pins on power off (VCC = 0V)
Simplified Functional Diagram
© 2002 National Semiconductor Corporation DS101336
10133601
www.national.com
1 page  
Applications Information (Continued)
existing RS-422 drivers. The TRI-STATE function allows the
driver outputs to be disabled, thus obtaining an even lower
power state when the transmission of data is not required.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recom-
mended practices are:
• Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS
port side) connector as possible.
• Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Three or more high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in
parallel should be used between each VCC and ground.
Multiple vias should be used to connect VCC and Ground
planes to the pads of the by-pass capacitors.
In addition, it may be necessary to randomly distribute
by-pass capacitors of different values (200pF to 1000pF)
to achieve different resonant frequencies.
• Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• The backplane and connectors should have a matched
differential impedance. Use controlled impedance traces
which match the differential impedance of your transmis-
sion medium (ie. backplane or cable) and termination
resistor(s). Run the differential pair trace lines as close
together as possible as soon as they leave the IC . This
will help eliminate reflections and ensure noise is coupled
as common-mode. In fact, we have seen that differential
signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is
much better with the closer traces. Plus, noise induced
on the differential lines is much more likely to appear as
common-mode which is rejected by the receiver. Match
electrical lengths between traces to reduce skew. Skew
between the signals of a pair means a phase difference
between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will re-
sult. (Note the velocity of propagation, v = c/Er where c
(the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do
not rely solely on the autoroute function for differential
traces. Carefully review dimensions to match differential
impedance and provide isolation for the differential lines.
Minimize the number of vias and other discontinuity on
the line. Avoid 90˚ turns (these cause impedance discon-
tinuity). Use arcs or 45˚ bevels. Within a pair of traces,
the distance between the two traces should be minimized
to maintain common-mode rejection of the receivers. On
the printed circuit board, this distance should remain
constant to avoid discontinuity in differential impedance.
Minor violations at connection points are allowable.
• Stub Length: Stub lengths should be kept to a minimum.
The typical transition time of the DS92LV040A BLVDS
output is 0.75ns (20% to 80%). The extrapolated 100
percent time is 0.75/0.6 or 1.25ns. For a general approxi-
mation, if the electrical length of a trace is greater than
1/5 of the transition edge, then the trace is considered a
transmission line. For example, 1.25ns/5 is 250 picosec-
onds. Let velocity equal 160ps per inch for a typical
loaded backplane. Then maximum stub length is 250ps/
160ps/in or 1.56 inches. To determine the maximum stub
for your backplane, you need to know the propagation
velocity for the actual conditions (refer to application
notes AN 905 and AN 808).
PACKAGE and SOLDERING INFORMATION:
• Refer to packaging application note AN-1187. This appli-
cation note details the package attachment methods to
achieve the correct solderability and thermal results.
5 www.national.com
5 Page 
Pinout Description
Pin Name
DO+/RI+
DO−/RI−
DIN
RO
RE12
Pin #
14, 16, 19, 21
13, 15, 18, 20
35, 37, 40, 42
36, 38, 41, 43
29
RE34
5
DE12
26
DE34
8
GND
VCC
AGND
AVCC
NC
DAP
4, 28, 31, 39
3, 6, 30
9, 17, 25
7, 10, 22, 27
1, 2, 11, 12, 23, 24,
32, 33, 34, 44
Input/Output
I/O
I/O
I
O
I
I
I
I
Ground
Power
Ground
Power
N/A
Descriptions
True Bus LVDS Driver Outputs and Receiver Inputs.
Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
LVTTL Driver Input. No pull up or pull down is attached to this pin
LVTTL Receiver Output.
Receiver Enable LVTTL Input (Active Low). This pin, when low,
configures receiver outputs, RO1 and RO2 active. When this pin is
high, RO1 and RO2 are TRI-STATE. If this pin is floating, a weak
current source to VCC causes RO1 and RO2 to be TRI-STATE
Receiver Enable LVTTL Input (Active Low). This pin, when low,
configures receiver outputs, RO3 and RO4 active. When this pin is
high, RO3 and RO4 are TRI-STATE. If this pin is floating, a weak
current source to VCC causes RO3 and RO4 to be TRI-STATE
Driver Enable LVTTL Input (Active High). This pin, when high,
configures driver outputs, DO1+/RIN1+, DO1−/RIN1− and
DO2+/RIN2+, DO2−/RIN2− active. When this pin is low, driver outputs
1 and 2 are TRI-STATE. If this pin is floating, a weak current source
to VCC causes driver outputs 1 and 2 to be active
Driver Enable LVTTL Input (Active High). This pin, when high,
configures driver outputs, DO3+/RIN3+, DO3−/RIN3− and
DO4+/RIN4+, DO4−/RIN4− active. When this pin is low, driver outputs
3 and 4 are TRI-STATE. If this pin is floating, a weak current source
to VCC causes driver outputs 3 and 4 to be active
Ground for digital circuitry (must connect to GND on PC board). These
pins connected internally.
VCC for digital circuitry (must connect to VCC on PC board). These
pins connected internally.
Ground for analog circuitry (must connect to GND on PC board).
These pins connected internally.
Analog VCC (must connect to VCC on PC board). These pins
connected internally.
Reserved for future use, leave open circuit.
GND
Must connect to GND plane through vias to achieve the theta ja
specified under Absolute Maximum Ratings. The DAP (die attach pad)
is the heat transfer material that is centered on the bottom of the LLP
package. Refer to application note AN-1187 for attachment details.
11 www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS92LV040A.PDF ] | |
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