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PDF DS90CR217MTD Data sheet ( Hoja de datos )
| Número de pieza | DS90CR217MTD | |
| Descripción | +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1999
DS90CR217/DS90CR218
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link - 75 MHz
General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR218 receiver converts the
three LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 75 MHz, 21 bits of TTL
data are transmitted at a rate of 525 Mbps per LVDS data
channel. Using a 75 MHz clock, the data throughput is 1.575
Gbit/s (197 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 75 MHz shift clock support
n 50% duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on TxINPUTs and
RxOUTPUTs
n Low power consumption
n Tx + Rx Power-down mode <400µW (max)
n ±1V common mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 1.575 Gbps throughput
n Up to 197 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
Block Diagrams
DS90CR217
DS90CR218
Order Number DS90CR217MTD
See NS Package Number MTD48
DS100871-1
Order Number DS90CR218MTD
See NS Package Number MTD48
DS100871-27
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100871
www.national.com
1 page  
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
Receiver Input Strobe Position for Bit 0 (Figure 16)
f = 75 MHz
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 17)
f = 75 MHz
RxCLK OUT Period (Figure 7)
RxCLK OUT High Time (Figure 7)
f = 75 MHz
RxCLK OUT Low Time (Figure 7)
RxOUT Setup to RxCLK OUT (Figure 7)
RxOUT Hold to RxCLK OUT (Figure 7)
RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 3.3V (Note 6)(Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 14)
Min
0.58
2.49
4.39
6.30
8.20
10.11
12.01
380
13.33
3.6
3.6
3.5
3.5
3.4
Typ
2.0
1.8
0.95
2.86
4.76
6.67
8.57
10.48
12.38
T
5
5
5.0
Max
3.5
3.5
1.32
3.23
5.13
7.04
8.94
10.85
12.75
50
6.0
6.0
7.3
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and source clock jitter less than 250 ps.
Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288 receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS100871-2
DS100871-3
FIGURE 2. DS90CR217 (Transmitter) LVDS Output Load and Transition Times
DS100871-4
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typicaIIy 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 75MHz
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 17. Receiver LVDS Input Skew Margin
DS100871-20
Applications Information
The DS90CR217 and DS90CR218 are backward compatible
with the existing 5V Channel Link transmitter/receiver pair
(DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V
system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL V CC.
2. Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
3. The receiver powerdown feature when enabled wilI lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
DS90CR217 Pin Description — Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V CC
GND
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I/O No.
I 21
O3
O3
I1
O1
O1
I1
I4
I5
I1
I2
I1
I3
Description
TTL level input.
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pins for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90CR218 Pin Description — Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
I/O No.
Description
I 3 Positive LVDS differential data inputs. (Note 12)
I 3 Negative LVDS differential data inputs. (Note 12)
O 21 TTL level data outputs.
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
11 www.national.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet DS90CR217MTD.PDF ] | |
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