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PDF DS90CR216MTD Data sheet ( Hoja de datos )
| Número de pieza | DS90CR216MTD | |
| Descripción | +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 1999
DS90CR215/DS90CR216
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link - 66 MHz
General Description
The DS90CR215 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR216 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 66 MHz, 21 bits of TTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s
(173 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 21-bit wide
data and one clock, up to 44 conductors are required. With
the Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables’ smaller form factor.
The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, five 4-bit nibbles plus 1 control,
or two 9-bit (byte + parity) and 3 control.
Features
n Single +3.3V supply
n Chipset (Tx + Rx) power consumption <250 mW (typ)
n Power-down mode (<0.5 mW total)
n Up to 173 Megabytes/sec bandwidth
n Up to 1.386 Gbps data throughput
n Narrow bus reduces cable size
n 290 mV swing LVDS devices for low EMI
n +1V common mode range (around +1.2V)
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n ESD Rating > 7 kV
n Operating Temperature: −40˚C to +85˚C
Block Diagrams
DS90CR215
DS90CR216
Order Number DS90CR215MTD
See NS Package Number MTD48
DS012909-1
DS012909-27
Order Number DS90CR216MTD
See NS Package Number MTD48
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012909
www.national.com
1 page  
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min Typ
TPPos3
Transmitter Output Pulse Position for
Bit3
10.2
10.4
TPPos4
Transmitter Output Pulse Position for
Bit4
13.7
13.9
TPPos5
Transmitter Output Pulse Position for
Bit5
17.3
17.6
TPPos6
Transmitter Output Pulse Position for
Bit6
21.0
21.2
TPPos0
Transmitter Output Pulse Position for
Bit0 (Note 6) (Figure 16)
f = 66 MHz
−0.4
0
TPPos1
Transmitter Output Pulse Position for
Bit1
1.8 2.2
TPPos2
Transmitter Output Pulse Position for
Bit2
4.0 4.4
TPPos3
Transmitter Output Pulse Position for
Bit3
6.2 6.6
TPPos4
Transmitter Output Pulse Position for
Bit4
8.4 8.8
TPPos5
Transmitter Output Pulse Position for
Bit5
10.6
11.0
TPPos6
Transmitter Output Pulse Position for
Bit6
12.8
13.2
TCIP
TxCLK IN Period (Figure 6)
15 T
TCIH
TxCLK IN High Time (Figure 6)
0.35T
0.5T
TCIL
TxCLK IN Low Time (Figure 6)
0.35T
0.5T
TSTC
TxIN Setup to TxCLK IN (Figure 6)
2.5
THTC
TxIN Hold to TxCLK IN (Figure 6)
0
TCCD
TxCLK IN to TxCLK OUT Delay @ 25˚C,VCC=3.3V
(Figure 8)
3 3.7
TPLLS
Transmitter Phase Lock Loop Set (Figure 10)
TPDD
Transmitter Powerdown Delay (Figure 14)
Max
11.0
14.6
18.2
21.8
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
5.5
10
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min Typ Max Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3)
2.2 5.0 ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3)
2.2 5.0 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Note 7)(Figure 17) f = 40 MHz
1.0 1.4 2.15 ns
RSPos1 Receiver Input Strobe Position for Bit 1
4.5 5.0 5.8 ns
RSPos2 Receiver Input Strobe Position for Bit 2
8.1 8.5 9.15 ns
RSPos3 Receiver Input Strobe Position for Bit 3
11.6 11.9 12.6
ns
RSPos4 Receiver Input Strobe Position for Bit 4
15.1 15.6 16.3
ns
RSPos5 Receiver Input Strobe Position for Bit 5
18.8 19.2 19.9
ns
RSPos6 Receiver Input Strobe Position for Bit 6
22.5 22.9 23.6
ns
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
FIGURE 17. Receiver LVDS Input Strobe Position
DS012909-28
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS90CR216MTD.PDF ] | |
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