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PDF DS90CF364AMTD Data sheet ( Hoja de datos )
| Número de pieza | DS90CF364AMTD | |
| Descripción | +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link65 MHz/ +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link65 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 2006
DS90CF384A/DS90CF364A
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link—65 MHz
General Description
The DS90CF384A receiver converts the four LVDS data
streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec
bandwidth) back into parallel 28 bits of CMOS/TTL data (24
bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also
available is the DS90CF364A that converts the three LVDS
data streams (Up to 1.3 Gbps throughput or 170 Megabytes/
sec bandwidth) back into parallel 21 bits of CMOS/TTL data
(18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both
Receivers’ outputs are Falling edge strobe. A Rising edge or
Falling edge strobe transmitter (DS90C383A/DS90C363A)
will interoperate with a Falling edge strobe Receiver without
any translation logic.
The DS90CF384A / DS90CF364A devices are enhanced
over prior generation receivers and provided a wider data
valid time on the receiver output.
The DS90CF384A is also offered in a 64 ball, 0.8mm fine
pitch ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the 56L TSSOP
package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support
n 50% duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on RxOUTPUTs
n Rx power consumption <142 mW (typ) @65MHz
Grayscale
n Rx Power-down mode <200µW (max)
n ESD rating >7 kV (HBM), >700V (EIAJ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
n DS90CF384A is also available in a 64 ball, 0.8mm fine
pitch ball grid array (FBGA) package
Block Diagrams
DS90CF384A
DS90CF364A
10087027
Order Number DS90CF384AMTD or DS90CF384ASLC
See NS Package Number MTD56 or SLC64A
Order Number DS90CF364AMTD
See NS Package Number MTD48
10087028
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS100870
www.national.com
1 page  
AC Timing Diagrams (Continued)
10087003
FIGURE 3. “16 Grayscale” Test Pattern (DS90CF364A)(Notes 5, 6, 7, 8)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
10087004
FIGURE 4. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times
10087005
FIGURE 5. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times
5
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5 Page 
DS90CF384A Pin Descriptions — 56L TSSOP Package — 24-Bit FPD Link
Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I4
I4
O 28
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control
lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data
Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
DS90CF364A Pin Descriptions — 48L TSSOP Package — 18-Bit FPD Link
Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I3
I3
O 21
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
11 www.national.com
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| PDF Descargar | [ Datasheet DS90CF364AMTD.PDF ] | |
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