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PDF DS90C402 Data sheet ( Hoja de datos )
| Número de pieza | DS90C402 | |
| Descripción | Dual Low Voltage Differential Signaling (LVDS) Receiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1998
DS90C402
Dual Low Voltage Differential Signaling (LVDS) Receiver
General Description
The DS90C402 is a dual receiver device optimized for high
data rate and low power applications. This device along with
the DS90C401 provides a pair chip solution for a dual high
speed point-to-point interface. The device is in a PCB space
saving 8 lead small outline package. The receiver offers
±100 mV threshold sensitivity, in addition to common-mode
noise protection.
Features
n Ultra Low Power Dissipation
n Operates above 155.5 Mbps
n Standard TIA/EIA-644
n 8 Lead SOIC Package saves PCB space
n VCM ±1V center around 1.2V
n ±100 mV Receiver Sensitivity
Connection Diagram
Functional Diagram
DS100006-1
Order Number DS90C402M
See NS Package Number M08A
DS100006-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100006
www.national.com
1 page  
Ordering Information
Operating
Temperature
−40˚C to +85˚C
Package Type/
Number
SOP/M08A
Order Number
DS90C402M
RECEIVE MODE
RIN+ − RIN−
> +100 mV
< −100 mV
100 mV > & > −100 mV
ROUT
H
L
X
H = Logic High Level
L = Logic Low level
X = Indeterminant State
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise speci-
fied.
Note 3: All typicals are given for: VCC = +5.0V, TA = +25˚C.
Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN.
Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event
on the inputs.
Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
Note 7: ESD Rating:
HBM (1.5 kΩ, 100 pF) ≥ 3,500V
EIAJ (0Ω, 200 pF) ≥ 250V
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not ex-
ceed maximum junction temperature specification.
Note 9: CL includes probe and jig capacitance.
Typical Performance Characteristics
Output High Voltage vs
Power Supply Voltage
Output High Voltage vs
Ambient Temperature
DS100006-9
DS100006-10
5 www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet DS90C402.PDF ] | |
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