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PDF DS90C2501 Data sheet ( Hoja de datos )
| Número de pieza | DS90C2501 | |
| Descripción | Transmitter with built-in scaler for LVDS Display Interface (LDI) | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2003
DS90C2501
Transmitter with built-in scaler for LVDS Display
Interface (LDI)
General Description
The DS90C2501 is a highly integrated scaling IC with LVDS
transmitter with a scaled resolution up to SXGA+ for single
pixel input. The DS90C2501 is a video controller hub de-
signed to be compatible with Graphic Memory Controller
Hub (GMCH). The input interface can be single or dual DVO
port (12 pin per port). The high quality cubic zoom engine
scales the input graphics into the desired/optimal output
resolution up to 1400x1050 resolution. Advanced video digi-
tal signal processing provides gamma correction, and dith-
ering for the display output. A two-wire serial interface is
used to communicate with the host system. The dual high
speed LVDS channels supports single pixel in-single pixel
out, single pixel in-dual pixel out, and dual pixel in-dual pixel
out transmission modes. The DS90C2501 complies to Open
LDI standard, and can be paired up with DS90CF388 re-
ceiver or FPD8531x/FPD8731x series integrated timing con-
troller or FPDLink LVDS receivers such as DS90CF364/
DS90CF384A/DS90CF384/DS90CF384A. The LVDS output
is similar to DS90C387 and DS90C387R. Thus, this trans-
mitter can be paired up with DS90CF388, receiver of
112MHz LDI chipset or FPD-Link Receivers in non-DC Bal-
ance mode operation which provides GUI/LCD panel/mother
board vendors a wide choice of inter-operation with LVDS
based TFT panels.
This chip is an ideal solution to solve EMI and cable size
problems for high-resolution flat panel applications. It pro-
vides a reliable industry standard interface based on LVDS
technology that delivers the bandwidth needed for high-
resolution panels while maximizing bit times, and keeping
clock rates low to reduce EMI and shielding requirements.
For more details, please refer to the “Applications Informa-
tion” section of this datasheet.
Features
n Complies with Open LDI and GMCH DVO specification
for digital display interfaces
n 25 to 65 MHz clock in single pixel in to single pixel out
operation.
n 50 to 130 MHz clock in single pixel in to dual pixel out
operation.
n Support 24bit/48bit color TFT LCD with Conventional
and Non-Conventional Color Mappings.
n Support 16bit/32bit color TFT LCD.
n Single pixel transmitter inputs support single pixel GUI
interface.
n Up scaling/panel fitting supports VGA to SXGA+ output
in single pixel input mode at 640x480@60Hz,
800x600@60Hz, 1024x768@60Hz, 1280x1024@60Hz,
1400x1050@60Hz.
n Independent horizontal and vertical scaling.
n Support dithering (available for 6-bit color only),
programmable smoothing and anti-aliasing filter.
n Programmable digital sharpness, edge enhancement
and contrast control via gamma correction.
n Allow 2% at 200KHz spread spectrum clocking, rejects
cycle-to-cycle jitter (+/− 20% of input data bit time).
n Programmable LCD panel power sequencing.
n Support low voltage swing signal level (1V to 1.8V),
2.5V and 3.3V LVTTL level on CLKINP, CLKINM, D0 to
D23, DE, HSYNC and VSYNC pins
n Support 2.5V/3.3V LVTTL level on configuration pins
n Support 3.3V LVTTL level on GPIO pins
n Available in 10mm x 10mm x 1mm 128pin thermally
enhanced CSP package.
n Two-wire serial communication interface is active during
normal as well as power down mode and support data
rates up to 400KHz.
n TIA/EIA-644, Open LDI, DVO compliance.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
DVO is a registered trademark of Intel Corporation.
AGP or 4x AGP is a registered trademark of Intel Corporation.
© 2003 National Semiconductor Corporation DS200045
www.national.com
1 page  
Two-Wire Serial Communication Interface
Unless otherwise noted, below specifications apply for VCC3V pin = 3.0V to 3.6V.
Symbol
Parameter
Conditions
Min
VIN(1)
VIN(0)
VOL
Logical “ 1 ” input voltage
Logical “ 0 ” input voltage
Serial Bus Low level output
voltage
IOL = 3mA
2.1
IOL = 6mA
Typ
0.1
0.15
Recommended DVO Port Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
TCIT
TxCLK IN Transition Time (Figure 4)
DUAL = Gnd
0.8
TCIP
TxCLK IN Period (Figure 5)
DUAL = Gnd
5.9
TCIH
TxCLK in High Time (Figure 5)
0.35T
TCIL
TxCLK in Low Time (Figure 5)
0.35T
TXIT
D0 to D23 Transition Time
VDDQ
Low Swing Voltage Amplitude from GMCH
1.0
Typ
1.2
T
0.5T
0.5T
1
Max
0.8
0.4
0.6
Units
V
V
V
V
Max
2.4
40
0.65T
0.65T
1.8
Units
ns
ns
ns
ns
ns
V
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference) (Note 10)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 10: ISI is dependent on interconnect length; may be zero
FIGURE 10. Receiver Skew Margin
20004525
20004508
FIGURE 11. Resistor Network for “DUAL” pin input - recommend using R1=R2=10kΩ ±1% for single to dual mode
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS90C2501.PDF ] | |
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