|
|
PDF DS90C032BTM Data sheet ( Hoja de datos )
| Número de pieza | DS90C032BTM | |
| Descripción | LVDS Quad CMOS Differential Line Receiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS90C032BTM (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
March 1999
DS90C032B
LVDS Quad CMOS Differential Line Receiver
General Description
The DS90C032B is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE® function
that may be used to multiplex outputs. The receiver also sup-
ports OPEN and terminated (100Ω) input Fail-safe. Receiver
output will be HIGH for both Fail-safe conditions.
The DS90C032B provides power-off high impedance LVDS
inputs. This feature assures minimal loading effect on the
LVDS bus lines when VCC is not present.
The DS90C032B and companion line driver (DS90C031B)
provide a new alternative to high power pseudo-ECL devices
for high speed point-to-point interface applications.
Features
n >155.5 Mbps (77.7 MHz) switching rates
n Accepts small swing (350 mV) differential signal levels
n High Impedance LVDS inputs with power down
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
n Industrial operating temperature range
n Available in surface mount packaging (SOIC)
n Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL)
n Supports OPEN and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
Dual-In-Line
Functional Diagram
DS100990-1
Order Number
DS90C032BTM
See NS Package
Number M16A
Receiver Truth Table
ENABLES
EN EN*
LH
All other combinations
of ENABLE inputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100990
DS100990-2
INPUTS
RIN+ − RIN−
X
VID ≥ 0.1V
VID ≤ −0.1V
Fail-safe OPEN
or Terminated
OUTPUT
ROUT
Z
H
L
H
www.national.com
1 page  
Typical Application
DS100990-7
FIGURE 5. Point-to-Point Application
Applications Information
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 5. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic im-
pedance of the media is in the range of 100Ω. A termination
resistor of 100Ω should be selected to match the media, and
is located as close to the receiver input pins as possible. The
termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90C032B differential line receiver is capable of de-
tecting signals as low as 100 mV, over a ±1V common-mode
range centered around +1.2V. This is related to the driver off-
set voltage which is typically +1.2V. The driven signal is cen-
tered around this voltage and may shift ±1V around this cen-
ter point. The ±1V shifting may be the result of a ground
potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. Both re-
ceiver input pins should honor their specified operating input
voltage range of 0V to +2.4V (measured from each pin to
ground), exceeding these limits may turn on the ESD protec-
tion circuitry which will clamp the bus voltages.
Receiver Fail-Safe:
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating or terminated receiver inputs.
1. Open Input Pins. The DS90C032B is a quad receiver
device, and if an application requires only 1, 2 or 3 re-
ceivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a TRI-STATE or
power-off condition, the receiver output will again be in a
HIGH state, even with the end of cable 100Ω termination
resistor across the input pins. The unplugged cable can
become a floating antenna which can pick up noise. If
the cable picks up more than 10mV of differential noise,
the receiver may see the noise as a valid signal and
switch. To insure that any noise is seen as
common-mode and not differential, a balanced intercon-
nect should be used. Twisted pair cable will offer better
balance than flat ribbon cable.
The footprint of the DS90C032B is the same as the industry
standard 26LS32 Quad Differential (RS-422) Receiver.
For additional LVDS application information, please refer to
National’s LVDS Owner’s Manual available through Nation-
al’s website www.national.com/appinfo/lvds.
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
5 www.national.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet DS90C032BTM.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90C032BTM | LVDS Quad CMOS Differential Line Receiver | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |