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PDF DS90C031B Data sheet ( Hoja de datos )
| Número de pieza | DS90C031B | |
| Descripción | LVDS Quad CMOS Differential Line Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 1999
DS90C031B
LVDS Quad CMOS Differential Line Driver
General Description
The DS90C031B is a quad CMOS differential line driver de-
signed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support data
rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Volt-
age Differential Signaling (LVDS) technology.
The DS90C031B accepts TTL/CMOS input levels and trans-
lates them to low voltage (350 mV) differential output sig-
nals. In addition the driver supports a TRI-STATE® function
that may be used to disable the output stage, disabling the
load current, and thus dropping the device to an ultra low idle
power state of 11 mW typical.
In addition, the DS90C031B provides power-off high imped-
ance LVDS outputs. This feature assures minimal loading ef-
fect on the LVDS bus lines when VCC is not present.
The DS90C031B and companion line receiver (DS90C032B)
provide a new alternative to high power pseudo-ECL devices
for high speed point-to-point interface applications.
Features
n >155.5 Mbps (77.7 MHz) switching rates
n High impedance LVDS outputs with power-off
n ±350 mV differential signaling
n Ultra low power dissipation
n 400 ps maximum differential skew (5V, 25˚C)
n 3.5 ns maximum propagation delay
n Industrial operating temperature range
n Pin compatible with DS26C31, MB571 (PECL) and
41LG (PECL)
n Conforms to ANSI/TIA/EIA-644 LVDS standard
n Offered in narrow and wide body SOIC package
n Fail-safe logic for floating inputs
Connection Diagram
Dual-In-Line
Functional Diagram
DS100989-1
Order Number
DS90C031BTM,
or DS90C031BTWM
See NS Package Number
M16A or M16B
Driver Truth Table
Enables
EN
L
All other combinations
of ENABLE inputs
EN*
H
DS100989-2
Input
DIN
X
L
H
Outputs
DOUT+
Z
DOUT−
Z
LH
HL
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100989
www.national.com
1 page  
Parameter Measurement Information (Continued)
Typical Application
FIGURE 5. Driver TRI-STATE Delay Waveform
DS100989-7
DS100989-8
FIGURE 6. Point-to-Point Application
Applications Information
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic im-
pedance of the media is in the range of 100Ω. A termination
resistor of 100Ω should be selected to match the media, and
is located as close to the receiver input pins as possible. The
termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90C031B differential line driver is a balanced current
source design. A current mode driver, generally speaking
has a high output impedance and supplies a constant cur-
rent for a range of loads (a voltage mode driver on the other
hand supplies a constant voltage for a range of loads). Cur-
rent is switched through the load in one direction to produce
a logic state and in the other direction to produce the other
logic state. The typical output current is a mere 3.4 mA with
a minimum of 2.5 mA, and a maximum of 4.5 mA. The cur-
rent mode requires (as discussed above) that a resistive ter-
mination be employed to terminate the signal and to com-
plete the loop as shown in Figure 6. AC or unterminated
configurations are not allowed. The 3.4 mA loop current will
develop a differential voltage of 340 mV across the 100Ω ter-
mination resistor which the receiver detects with a 240 mV
minimum differential noise margin neglecting resistive line
losses (driven signal minus receiver threshold (340 mV –
100 mV = 240 mV). The signal is centered around +1.2V
(Driver Offset, VOS) with respect to ground as shown inFig-
ure 7. Note that the steady-state voltage (VSS) peak-to-peak
swing is twice the differential voltage (VOD) and is typically
680 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the cur-
rent mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
ICC requirements of the ECL/PECL designs. LVDS requires
80% less current than similar PECL devices. AC specifica-
tions for the driver are a tenfold improvement over other ex-
isting RS-422 drivers.
The fail-safe circuitry guarantees that the outputs are en-
abled and at a logic ’0’ (the true output is low and the
complement output is high) when the inputs are floating.
5 www.national.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90C031BTM
NS Package Number M16A
11 www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS90C031B.PDF ] | |
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