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PDF DS80C390-FNR Data sheet ( Hoja de datos )
| Número de pieza | DS80C390-FNR | |
| Descripción | Dual CAN High-Speed Microprocessor | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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PRELIMINARY
DS80C390
Dual CAN High-Speed
Microprocessor
FEATURES
§ 80C52 compatible
− 8051 instruction-set compatible
− Four 8-bit I/O ports
− Three 16-bit timer/counters
− 256 bytes scratchpad RAM
§ High-Speed Architecture
− 4 clocks/machine cycle (8051=12)
− Runs DC to 40 MHz clock rates
− Frequency multiplier reduces EMI
− Single-cycle instruction in 100 ns
− 16/32-bit math coprocessor
§ 4 kB internal SRAM usable as
program/data/stack memory
§ Enhanced memory architecture
− Addresses up to 4 MB external
− Defaults to true 8051 memory compatibility
− User-enabled 22-bit program/data counter
− 16-Bit/22-bit paged/22-bit contiguous
modes
− User-selectable multiplexed / non-
multiplexed memory interface
− Optional 10 bit stack pointer
§ Two full-function CAN 2.0B controllers
− 15 message centers per controller
− Standard 11-bit or extended 29-bit
identification modes
− Supports DeviceNet, SDS, and higher layer
CAN protocols
− Disables transmitter during autobaud
− SIESTA low power mode
§ Two full-duplex hardware serial ports
§ Programmable IrDA clock
§ High integration controller includes
− Power-fail reset
− Early-warning power-fail interrupt
− Programmable watchdog timer
− Oscillator-fail detection
§ 16 total interrupt sources with 6 external
§ Available in 64-pin QFP, 68-pin PLCC
PIN ASSIGNMENT
48
49
33
DS80C390
64
1 16
64-PIN QFP
9
10
1 61
DS80C390
26
27 43
68-PIN PLCC
32
17
60
44
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4-7,
10-13
4
5
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7
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2-8, 10
2
3
4
5
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8
10
46
47
48
49
50
53
54
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13-16,
19-22
13
14
15
16
19
20
21
P1.0-P1.7
A0
A1
A2
A3
A4
A5
A6
A7
A8 (P2.0)
A9 (P2.1)
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
P3.0-P3.7
DS80C390
Port 1 - I/O. Port 1 can function as an 8-bit bi-directional I/O port,
the non-multiplexed A0 - A7 signals (when the MUX pin =1), and
as an alternate interface for internal resources. Setting the SP1EC
bit relocates RXD1 and TXD1 to Port 5. The reset condition of Port
1 is all bits at logic 1 via a weak pullup. The logic 1 state also
serves as an input mode, since external circuits writing to the port
can overdrive the weak pullup. When software clears any port pin
to 0, a strong pulldown is activated that remains on until either a 1
is written to the port pin or a reset occurs. Writing a 1 after the port
has been at 0 will activate a strong transition driver, followed by a
weaker sustaining pullup. Once the momentary strong driver turns
off, the port once again becomes the output (and input) high state.
Port Alternate Function
P1.0 T2 External I/O for Timer/Counter 2
P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1 Serial Port 1 Input
P1.3 TXD1 Serial Port 1 Output
P1.4 INT2 External Interrupt 2 (Pos. Edge Detect)
P1.5 INT3 External Interrupt 3 (Neg. Edge Detect)
P1.6 INT4 External Interrupt 4 (Pos. Edge Detect)
P1.7 INT5 External Interrupt 5 (Neg. Edge Detect)
A15-A8 (Port 2) - Output. Port 2 serves as the MSB for external
addressing. The port automatically asserts the address MSB during
external ROM and RAM access. Although the Port 2 SFR exists,
the SFR value will never appear on the pins (due to memory
access). Therefore accessing the Port 2 SFR is only useful for
MOVX A, @Ri or MOVX @Ri, A instructions, which use the Port
2 SFR as the external address MSB.
Port 3 - I/O. Port 3 functions as an 8-bit bi-directional I/O port,
and as an alternate interface for several resources found on the
traditional 8051. The reset condition of Port 1 is all bits at logic 1
via a weak pullup. The logic 1 state also serves as an input mode,
since external circuits writing to the port can overdrive the weak
pullup. When software clears any port pin to 0, the device activates
a strong pulldown that remains on until either a 1 is written to the
port pin or a reset occurs. Writing a 1 after the port has been at 0
will activate a strong transition driver, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the
port once again becomes the output (and input) high state.
Port Alternate Function
P3.0 RXD0 Serial Port 0 Input
P3.1 TXD0 Serial Port 0 Output
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
P3.4 T0 Timer 0 External Input
P3.5 T1/XCLK Timer 1 External Input/External Clock Output
P3.6 WR External Data Memory Write Strobe
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DS80C390
ARITHMETIC ACCELERATOR SEQUENCING
Divide (32/16 or 16/16)
Multiply (16x16)
Load MA with dividend LSB.
Load MB with multiplier LSB.
Load MA with dividendLSB+1*
Load MB with multiplier MSB.
Load MA with dividend LSB+2*
Load MA with multiplicand LSB.
Load MA with dividend MSB.
Load MA with multiplicand MSB.
Load MB with divisor LSB.
Poll the MST bit until cleared
Load MB with divisor MSB.
(6 machine cycles).
Poll the MST bit until cleared
Read MA for product MSB.
(9 machine cycles).
Read MA for product LSB+2.
Read MA to retrieve the quotient MSB.
Read MA for product LSB+1.
Read MA to retrieve the quotient LSB+2.
Read MA for product LSB.
Read MA to retrieve the quotient LSB+1.
Read MA to retrieve the quotient LSB.
Read MB to retrieve the remainder MSB.
Read MB to retrieve the remainder LSB.
*Not performed for 16 bit numerator.
Shift Right/Left
Normalize
Load MA with data LSB.
Load MA with data LSB.
Load MA with data LSB+1.
Load MA with data LSB+1.
Load MA with data LSB+2.
Load MA with data LSB+2.
Load MA with data MSB.
Load MA with data MSB.
Configure MCNT0 register as required
Configure MCNT0 register as required.
Poll the MST bit until cleared.
Poll the MST bit until cleared
(9 machine cycles)
(9 machine cycles).
Read MA for result MSB.
Read MA for mantissa MSB.
Read MA for result LSB+2.
Read MA for mantissa LSB+2.
Read MA for result LSB+1.
Read MA for mantissa LSB+1.
Read MA for result LSB.
Read MA for mantissa LSB.
Read MCNT0.4-MCNT0.0 for exponent.
40-BIT ACCUMULATOR
The accelerator also incorporates an automatic accumulator function, permitting the implementation of
multiply-and-accumulate and divide-and-accumulate functions without any additional delay. Each time
the accelerator is used for a multiply or divide operation, the result is transparently added to a 40-bit
accumulator. This can greatly increase speed of DSP and other high-level math operations.
The accumulator can be accessed any time the Multiply/Accumulate Status Flag (MCNT1 ;D2h) is
cleared. The accumulator is initialized by performing five writes to the Multiplier C Register (MC ;D5h),
LSB first. The 40-bit accumulator can be read by performing five reads of the Multiplier C Register,
MSB first.
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| Páginas | Total 58 Páginas | |
| PDF Descargar | [ Datasheet DS80C390-FNR.PDF ] | |
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