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PDF 100331 Data sheet ( Hoja de datos )

Número de pieza 100331
Descripción Low Power Triple D Flip-Flop
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! 100331 Hoja de datos, Descripción, Manual

August 1998
100331
Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CPC), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CPn), Direct
Set (SDn) and Direct Clear (CDn) inputs. Data enters a mas-
ter when both CPn and CPC are LOW and transfers to a
slave when CPn or CPC (or both) go HIGH. The Master Set,
Master Reset and individual CDn and SDn inputs override
the Clock inputs. All inputs have 50 kpull-down resistors.
Features
n 35% power reduction of the 100131
n 2000V ESD protection
n Pin/function compatible with 100131
n Voltage compensated operating range = −4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Logic Symbol
Pin Names
CP0–CP2
CPC
D0– D2
CD0–CD2
SDn
MR
MS
Q0-Q2
Q0– Q2
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
DS100300-1
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100300-2
DS100300-3
© 1998 National Semiconductor Corporation DS100300
www.national.com

1 page




100331 pdf
Test Circuits
FIGURE 1. AC Test Circuit
DS100300-6
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = Equal length 50impedance lines
RT = 50terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50to GND
CL = Fixture and stray capacitance 3 pF
FIGURE 2. Toggle Frequency Test Circuit
DS100300-7
5 www.national.com

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