PDF CXD3526GG Data sheet ( Hoja de datos )

Número de pieza	CXD3526GG
Descripción	Digital Signal Driver/Timing Generator
Fabricantes	Sony Corporation
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No Preview Available ! CXD3526GG Digital Signal Driver/Timing Generator Description The CXD3526GG incorporates digital signal processor type RGB driver, color shading correction and timing generator functions onto a single IC. Operation is possible with a system clock up to 85 [MHz] (max.).This IC can process video signals in bands up to XGA standard, and can output the timing signals for driving various Sony LCD panels such as XGA and SVGA. 144 pin BGA (Plastic) Features • Various picture quality adjustment functions such as user adjustment, white balance adjustment and gamma correction • OSD MIX, black frame processing, mute and limiter functions • LCD panel color shading correction function • Drives various Sony data projector LCD panels such as XGA and SVGA • Controls the CXA3562AR and CXA7000R sample- and-hold drivers • Line inversion and field inversion signal generation • Supports AC drive of LCD panels during no signal • On-chip serial interface • The data of gamma correction and color shading correction can be downloaded automatically from the external EEPROM. Absolute Maximum Ratings (VSS = 0V) • Supply voltage VDD1 VSS – 0.5 to +3.0 V VDD2 VSS – 0.5 to +4.0 V • Input voltage VI VSS – 0.5 to VDD2 + 0.5 V • Output voltage VO VSS – 0.5 to VDD2 + 0.5 V • Storage temperature Tstg –55 to +125 °C • Junction temperature Tj 125 °C Recommended Operating Conditions • Supply voltage VDD1 2.3 to 2.7 VDD2 3.0 to 3.6 • Operating temperature Topr –20 to +75 V V °C Applications LCD projectors and other video equipment Structure Silicon gate CMOS IC Note) Company names and product names indicated on this data sheet are the trademark or registered trademark of each company. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01X09A26 1 page CXD3526GG Pin No. Symbol 37 VSS 38 ROUT9 39 ROUT8 40 ROUT7 41 VST 42 HD2 43 HD3 44 VDD2 45 PRG 46 ENB 47 PO1 48 PO2 49 DWN 50 RIN8 51 RIN6 52 RIN3 53 RIN1 54 GIN5 55 GIN1 56 BIN8 57 BIN5 58 BIN2 59 ROSD1 60 GOSD1 61 BOSD1 62 HDIN 63 CLKPOL 64 VSS 65 TEST5 66 XCLR2 67 TEST6 68 HSCL 69 RSDA 70 HSDA 71 VSS 72 BOUT2 73 BOUT6 Input pin I/O Description processing for open status — GND — O Red data output — O Red data output — O Red data output — O Vertical display start timing pulse output — O Horizontal auxiliary pulse output 2 — O Horizontal auxiliary pulse output 3 — — I/O power supply — O 2-step precharge timing pulse output — O Gate enable pulse output — O Parallel output 1 — O Parallel output 2 — I/O Vertical scan direction switching signal I/O — I Red data input — I Red data input — I Red data input — I Red data input — I Green data input — I Green data input — I Blue data input — I Blue data input — I Blue data input — I OSD red data input — I OSD green data input — I OSD blue data input — I Horizontal sync signal input — I Internal clock polarity selection (High: inverted; Low: non-inverted) L — GND — — Test pin (Connect to VDD2.) — I External clear (Low: reset) H — Test pin (Connect to GND.) — I Serial bus clock (host I/F) — I/O Serial bus data I/O (external ROM I/F) — I/O Serial bus data I/O (host I/F) — — GND — O Blue data output — O Blue data output — –5– 5 Page CXD3526GG Description of Operation 1. Description of I/O Pins (a) System clear pins (XCLR1, XCLR2 and XCLR3) All internal circuits are initialized by setting XCLR1 (Pin 102) low. In addition, the internal PLL is initialized by setting XCLR2 (Pin 66) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 103) low. Initialization should be performed when power is turned on. (b) Sync signal input pins (HDIN and VDIN) Horizontal and vertical separate sync signals are input to HDIN (Pin 62) and VDIN (Pin 17), respectively. The CXD3526GG supports only non-interlace sync signals with a dot clock of 100MHz or less. (c) Master clock input pins (CLKP/CLKN, CLKC, CLKSEL and CLKPOL) Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The master clock input pins have two systems consisting of CLKP/CLKN (Pins 101 and 130) for small-amplitude differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 131) for CMOS level input. In addition, the clock path selection is performed with CLKSEL (Pin 100) and CLKPOL (Pin 63). The setting values are as follows. CLKSEL: 0 = CLKP and CLKN input; 1 = CLKC input CLKPOL: 0 = Input clock is non-inverted; 1 = Input clock is inverted (d) PLL setting pin (PLLDIV) PLLDIV (Pin 129) sets the divider setting of the internal phase compensation PLL circuit. The setting values for master clock frequency are as follows. PLLDIV: 0 = 55 to 100MHz; 1 = 27.5 to 55MHz Note that the frequency of the clock input to the CXD3526GG must be within the phase compensation PLL operating range, even during free running. (e) RGB signal input pins (RIN, GIN and BIN) These pins input RGB digital signals in 10 bits. The Red signal is input to RIN (Pins 4 to 6, 50 to 53 and 89 to 91), the Green signal to GIN (Pins 7, 8, 54, 55, 92, 93 and 123 to 125), and the Blue signal to BIN (Pins 9 to 12, 56 to 58 and 95 to 97) respectively. (f) OSD signal input pins (ROSD, GOSD, BOSD, YS and YM) These pins input OSD signals. The Red signal is input to ROSD (Pins 14 and 59), the Green signal to GOSD (Pins 15 and 60), and the Blue signal to BOSD (Pins 16 and 61) respectively. In addition, the YM signal is input to YM (Pin 98), and the YS signal to YS (Pin 99). – 11 – 11 Page

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