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PDF CXD3521GG Data sheet ( Hoja de datos )
| Número de pieza | CXD3521GG | |
| Descripción | Interface and Driver IC for LCD | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Interface and Driver IC for LCD
CXD3521GG
Description
The CXD3521GG is an interface and driver IC for
the color LCD module ACX704AKM/BKM.
128 pin TFBGA (Plastic)
Features
• Generates the color LCD module ACX704AKM/BKM
drive pulse.
• Supports standby mode
• Built-in 9-channel reference voltage driver
• Built-in common voltage driver
Applications
PDA, compact LCD monitor, etc.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage 1 VDD1 VSS – 0.3 to +4.6 V
• Supply voltage 2 VDD2 VSS – 0.3 to +6.0 V
• Input voltage
VI VSS – 0.3 to VDD + 0.3 V
• Output voltage VO VSS – 0.3 to VDD + 0.3 V
• Storage temperature
Tstg
–55 to +125
°C
Recommended Operating Conditions
• Supply voltage 1 VDD1
3.0 to 3.6
• Supply voltage 2 VDD2
4.7 to 5.3
• Operating temperature
Topr –25 to +75
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01408-PS
1 page  
Pin
No.
Symbol
I/O
Description
M7 B21
O Blue signal output
L7 B11
O Blue signal output
K7 B01
O Blue signal output
J7 XR31
O R31 signal inversion output
M6 XR21
O R21 signal inversion output
L6 XR11
O R11 signal inversion output
K6 XR01
O R01 signal inversion output
M5 XG31
O G31 signal inversion output
L5 XG21
O G21 signal inversion output
K5 XG11
O G11 signal inversion output
J5 XG01
O G01 signal inversion output
M4 XB31
O B31 signal inversion output
L4 XB21
O B21 signal inversion output
M3 XB11
O B11 signal inversion output
L3 XB01
O B01 signal inversion output
M12 TESTP
I Test input (Connect to GND.)
A12 TEST
I Test input (Connect to GND.)
M2 VST
O VST pulse output
L1 XVST
O VST pulse inversion output
K4 ENB
O ENB pulse output
K3 XENB
O ENB pulse inversion output
J4 VCK
O VCK pulse output
J3 XVCK
O VCK pulse inversion output
K2 HCK1
O HCK1 pulse output
K1 XHCK1
O HCK1 pulse inversion output
J2 HCK2
O HCK2 pulse output
J1 XHCK2
O HCK2 pulse inversion output
H4 HST1
O HST1 pulse output
H3 XHST1
O HST1 pulse inversion output
H2 HST2
O HST2 pulse output
H1 XHST2
O HST2 pulse inversion output
G4 OE1
O OE1 pulse output
G3 XOE1
O OE1 pulse inversion output
G2 OE2
O OE2 pulse output
G1 XOE2
O OE2 pulse inversion output
D8 XB32
O B32 signal inversion output
A7 XB22
O B22 signal inversion output
∗ DWN: Pull-down (typ. 180kΩ)
–5–
CXD3521GG
Input pin for
open status
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DWN∗
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5 Page 
Vertical System
VCK
50%
tVH
50%
tVL
50%
XVCK
50%
∆tV
50%
∆tV
CXD3521GG
VDD1
GND
VDD1
GND
DATA
HCK1
XHCK1
HCK2
XHCK2
DATA
50%
50%
50%
50%
VDD1
GND
VDD1
GND
50%
50%
50%
50%
tST1D
tSTX1U
tST2D
tSTX2U
tST1U
tSTX1D
tST2U
tSTX2D
VDD1
GND
VDD1
GND
VDD1
GND
– 11 –
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CXD3521GG.PDF ] | |
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