PDF CXD3511AQ Data sheet ( Hoja de datos )

Número de pieza	CXD3511AQ
Descripción	Digital Signal Driver/Timing Generator
Fabricantes	Sony Corporation
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No Preview Available ! CXD3511AQ Digital Signal Driver/Timing Generator Description The CXD3511AQ incorporates digital signal processor type RGB driver, color shading correction, selectable delay line and timing generator functions onto a single IC. Operation is possible with a system clock up to 200 [MHz] (max.). This IC can process video signals in bands up to UXGA standard, and can output the timing signals for driving various Sony LCD panels such as UXGA, SXGA and XGA. Features • Various picture quality adjustment functions such as user adjustment, white balance adjustment and gamma correction • OSD MIX, black frame processing, mute and limiter functions • LCD panel color shading correction function • Selectable delay line • Drives various Sony data projector LCD panels such as UXGA, SXGA and XGA • Controls the CXA3562AR and CXA7000R sample- and-hold drivers • Line inversion and field inversion signal generation • Supports AC drive of LCD panels during no signal Applications LCD projectors and other video equipment 240 pin QFP (Plastic) Absolute Maximum Ratings (VSS = 0V) • Supply voltage VDD1 VSS – 0.5 to +3.0 V VDD2 VSS – 0.5 to +4.0 V • Input voltage VI VSS – 0.5 to VDD1 + 0.5 V • Output voltage VO VSS – 0.5 to VDD1 + 0.5 V • Storage temperature Tstg –55 to +125 °C • Junction temperature Tj 125 °C Recommended Operating Conditions • Supply voltage VDD1 2.3 to 2.7 VDD2 3.0 to 3.6 • Operating temperature Topr –20 to +75 V V °C Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02401-PS 1 page CXD3511AQ Pin No. Symbol 38 CLKP 39 CLKN 40 VDD2 41 CLKSEL1 42 VDD1 43 VSS 44 CLKSEL2 45 PLLDIV 46 VSS 47 CLKOUT 48 VSS 49 B2OUT0 50 B2OUT1 51 B2OUT2 52 B2OUT3 53 B2OUT4 54 VDD2 55 VSS 56 B2OUT5 57 B2OUT6 58 B2OUT7 59 B2OUT8 60 B2OUT9 61 B1OUT0 62 B1OUT1 63 B1OUT2 64 B1OUT3 65 B1OUT4 66 VDD2 67 VSS 68 B1OUT5 69 B1OUT6 70 B1OUT7 71 B1OUT8 72 B1OUT9 73 G2OUT0 74 G2OUT1 Input pin I/O Description processing for open status I Clock input (small-amplitude differential input, positive polarity) — I Clock input (small-amplitude differential input, negative polarity) — — I/O power supply — I Input clock selection. (High: CLKC, Low: CLKP, CLKN) L — Internal operation power supply — — GND — I Internal clock path selection. (High: no frequency division, Low: frequency division) L I Internal PLL setting. (High: 55MHz or less, Low: 55MHz or more) L — GND — O Internal clock output (inverted output) — — GND — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 2) — — I/O power supply — — GND — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 2) — O Blue data output (port 1) — O Blue data output (port 1) — O Blue data output (port 1) — O Blue data output (port 1) — O Blue data output (port 1) — — I/O power supply — — GND — O Blue data output (port 1) — O Blue data output (port 1) — O Blue data output (port 1) — O Blue data output (port 1) — O Blue data output (port 1) — O Green data output (port 2) — O Green data output (port 2) — –5– 5 Page CXD3511AQ Electrical Characteristics DC Characteristics (Topr = –20 to +75°C, VSS = 0V) Item Symbol Applicable pins Conditions Min. Typ. Max. Unit Supply voltage VDD1 VDD2 — — 2.3 2.5 2.7 — 3.0 3.3 3.6 Input voltage 1 VIH1 VIL1 ∗1 CMOS input cell 2.0 –0.3 — VDD2 + 0.3 — 0.8 Input voltage 2 Input voltage 3 VIH2 VIL2 VC∗2 VIH3 VIL3 HDIN, VDIN, PCTL, CMOS Schmitt PCLK, PDAT0 to PDAT9 trigger input cell CLKP, CLKN Small-amplitude differential input 0.8VDD2 –0.3 1.718 1.868 VSS — VDD2 + 0.3 — 0.2VDD2 2.0 2.281 VC + 0.4 VDD2 VC – 0.4 2.131 V Output voltage VOH All output pins VOL — VDD2 – 0.5 — VDD2 — VSS — 0.2 Current consumption PD∗3 — CLKP = 200MHz — 2600 3120 mW ∗1 Input pins other than those indicated in items Input voltage 2 and Input voltage 3. ∗2 VIH3 > VC (max.) and VIL3 < VC (min.). ∗3 Tj [°C] ≥ Toprmax [°C] + θja [°C/W] × PD [W]. (Tj = 125 [°C], Toprmax = 75 [°C], θja = 16 [°C/W], when mounted on a 4-layer substrate) AC Characteristics (Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V) Item Clock input period Symbol — Applicable pins CLKP, CLKN, CLKC Conditions — Min. Typ. Max. Unit 5 —— Input setup time Input hold time tis tih RGB input, OSD input, HDIN, VDIN — — Output rise/fall delay time tor/tof ∗4 CL = 20pF Output rise/fall delay time tor/tof CLKOUT CL = 50pF Cross-point time difference ∆t HCK1, HCK2, DCK1, DCK1X, DCK2, DCK2X CL = 20pF HCK1 duty HCK2 duty th/(th + tl) tl/(th + tl) HCK1 HCK2 CL = 20pF CL = 20pF Phase compensation PLL operating frequency — PLLDIV = L — PLLDIV = H ∗4 Output pins other than CLKOUT, PO1 to PO5, RGT, XRGT and DWN. 2.5 1.5 2.0 2.5 –5.0 48 48 55 27.5 — — 4.0 4.5 — 50 50 — — — — 8.0 ns 8.5 5.0 52 % 52 100 MHz 55 – 11 – 11 Page

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