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PDF CXD3503R Data sheet ( Hoja de datos )
| Número de pieza | CXD3503R | |
| Descripción | Color Shading Correction IC for Liquid Crystal Projectors | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD3503R
Color Shading Correction IC for Liquid Crystal Projectors
Description
The CXD3503R is a color shading correction IC for
Sony data projectors. Used together with the Sony
LCD driver CXA2111R or CXA2112R, this IC corrects
color shading caused by the LCD panel structure or
the optical system. This IC has a built-in SRAM and
D/A converter, and 16 horizontal and 13 vertical
correction points can be set via a serial interface.
64 pin LQFP (Plastic)
Functions
• Generates the color shading correction signals for
the high-temperature polysilicon TFT LCD panels
used in Sony projectors
• Supports various SVGA, XGA and SXGA signals
using 1/2 dot clock input
• Vertical output signal interpolation using an internal
arithmetic circuit
• Automatic determination of eliminated lines during
pulse eliminator display when used together with
the Sony timing generator ICs CXD2464R or
CXD3500R
• Supports up/down and/or right/left inversion
• Supports LCD panel display area switching
conversion functions
• Standby and correction OFF functions
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage VDD VSS – 0.3 to +7.0
• Input voltage VI VSS – 0.3 to VDD + 0.3
• Output voltage VO VSS – 0.3 to VDD + 0.3
• Storage temperature
Tstg –55 to +125
• Operating temperature
Topr
–40 to +85
V
V
V
°C
°C
Recommended Operating Conditions
(Ta = –20 to +75°C, VSS = 0V)
Supply voltage VDD
4.5 to 5.5
V
Applications
Liquid crystal projectors, etc.
Structure
Silicon gate CMOS IC
Note) Company names and product names, etc. contained in these materials are trademarks or registered trademarks of the
respective companies.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99432-PS
1 page  
CXD3503R
Electrical Characteristics
DC Characteristics
Item Symbol
Supply voltage VDD
Input, output voltage VI, VO
Input voltage 1
VIH
VIL
Input voltage 2
VIH
VIL
Input voltage 3
VIH
VIL
Input voltage 4
VIH
VIL
Input voltage 5
VIH
VIL
Output voltage 1
VOH
VOL
Input leak current IIL
Output leak
current
IOZ
Pull-up resistor RUP
Pull-down resistor RDN
Current consumption IDD
(VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –40 to +85°C)
Conditions
CMOS input
Min.
4.5
VSS
0.7VDD
Typ.
5.0
CMOS input
With pull-up resistor
0.7VDD
CMOS input
0.7VDD
With pull-down resistor
TTL input
2.2
TTL Schmitt input
2.5
IOH = –4mA
VDD – 2.1
IOL = 4mA
VI = VDD, VSS
–10
During high impedance
output
–10
60
45
During 41MHz operation
120
90
60
Max.
5.5
VDD
Unit Applicable pins
V
V
V
0.3VDD
∗1
V
0.3VDD
∗4
V
0.3VDD
∗2
V
0.8
∗5
V
0.6
∗3
V
0.4
10 µA
10 µA
240 kΩ
180 kΩ
mA
∗6, ∗7
∗1, ∗3, ∗5
∗7
∗4
∗2
(INPUT)
∗1 CTRL, DACKI, DWN, HST, OLIM, RGT, SLCK, VST
∗2 TEST0, 1, 2
∗3 HSYNC, SCLK, SCTR, SDAT
∗4 XCLR
∗5 CKI
(OUTPUT)
∗6 DACKO
∗7 DOUT00 to 05, DOUT10 to 15, DOUT20 to 25
Note) AOUT0, 1 and 2, DACO0, 1 and 2, BFIN0, 1 and 2, VRH and VRL are not included in the DC characteristics.
–5–
5 Page 
CXD3503R
Description of Output Correction Signal Operation
Horizontal direction
The correction data set in the SRAM by serial transfer is arithmetically processed inside the IC to determine
the output position corresponding to the value set by serial register HP7 to 0 using the front edge of HSYNC as
the reference. Interpolation is not performed for the horizontal direction, and interpolated data is output at the
cycle set by serial register HINT7 to 0 for the vertical direction. In addition, the maximum amplitude of the
correction signal output voltage is determined by VRH (Pin 44) and VRL (Pin 40). The internal DAC outputs at
the resistive potential division (VRH to VRL: 213Ω typ.), so be sure to input to VRH and VRL via buffers having
current capacity.
HSYNC
DACKO/I
Set by HP7 to 0
Set by HINT7 to 0
DOUT
VRH
DACO
VRL
The internally generated digital data DOUT is input to the internal D/A converter, latched by the D/A converter
clock input from DACKI, and output from DACO2, 1 and 0 as an analog signal.
Note) If edges remain, these level differences may appear as vertical stripes. Therefore, when using this as a
correction signal, be sure to eliminate the edges using an LPF, etc. before input to the CXA2111R or
CXA2112R.
Vertical direction
The vertical correction points set in the SRAM are arithmetically processed inside the IC to output interpolated
data for the lines other than correction points.
n
fm, n
m
fm, n +
1
a
(fm + 1, n – fm, n)
fm, n +
2
a
(fm + 1, n – fm, n)
n+1
fm + 1, n
fm, n + 1 +
1
a
(fm + 1, n + 1 – fm, n + 1)
fm, n + 1 +
2
a
(fm + 1, n + 1 – fm, n + 1)
VINT line(s)
a' lines
m+1
fm,
n
+
a–
a
1
(fm + 1,
n
–
fm,
n)
fm,
n
+
1
+
a
–
a
1
(fm
+
1,
n
+
1
–
fm,
n
+
1)
fm + 1, n
fm + 1, n + 1
fm, n: Correction data for point (m, n)
Vertical correction point interval
Set by VINT4 to 0 and ANM5 to 0
Assuming ANM5 to 0 = a,
a' = VINT × a
– 11 –
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CXD3503R.PDF ] | |
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