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PDF CXD3500R Data sheet ( Hoja de datos )
| Número de pieza | CXD3500R | |
| Descripción | Timing Generator for LCD Panels | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Timing Generator for LCD Panels
CXD3500R
Description
The CXD3500R is a timing signal generator for
driving the LCD panels of Sony data projectors. This
chip has a built-in serial interface circuit which
supports various SXGA (skip scan display), XGA,
SVGA and VGA signals, and (double speed) NTSC
and PAL signals through external control from a
microcomputer, etc.
Direct drive of LCD panels is possible using 5V
drive.
Features
• Generates the drive pulses for the LCD panels of
Sony high-temperature polycrystalline silicon TFT
data projectors.
• Supports various SXGA, XGA, SVGA and VGA signals.
• Programmable output signals allow the optimal
pulse output settings for each panel.
• Programmable skip scan display allows skip scan
display of various signals (SXGA → XGA, XGA →
SVGA, Macintosh16 → SVGA, etc.)
• Supports NTSC and PAL signals with line double-
speed display using a built-in double-speed
controller. (clock frequency: 36MHz or less)
(Line memory: µPD485505: NEC)
• Allows control of sample-and-hold position of
CXA2112R sample-and-hold driver.
• Supports up/down inversion and/or right/left
inversion.
• Supports line inversion and field inversion.
• AC drive of LCD panels during no signal
64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
• Supply voltage VDD Vss – 0.5 to +7.0
V
• Input voltage
VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg –55 to +150
°C
Recommended Operating Conditions
• Supply voltage VDD
4.5 to 5.5
• Operating temperature
Topr
–20 to +75
V
°C
Applications
LCD projectors, etc.
Structure
Silicon gate CMOS IC
Note) "Macintosh" is a registered trademark of Apple Computer Inc.
"PC98" is a registered trademark of NEC Corp.
"VGA" is a registered trademark of IBM Corp.
Other company names and product names, etc. contained in these materials are trademarks or registered trademarks of the
respective companies.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99112-PS
1 page  
CXD3500R
Electrical Characteristics
1. DC characteristics
Item Symbol
Supply voltage
VDD
Input, output voltages VI, VO
Input voltage 1
VIH
VIL
Logical threshold value Vth
Input voltage 2
VIH
VIL
Input amplitude VIN
Feedback resistor RFB
Input voltage 3
VIH
VIL
VT+
Input voltage 4
VT–
VT+ – VT–
Output voltage 1
VOH
VOL
Output voltage 2
VOH
VOL
Output voltage 3
VOH
VOL
II
Input leak current IIL
II
Output leak
current
IOZ
Current consumption IDD
Conditions
TTL input
Small amplitude input
50MHz sine wave
VIN = Vss or VDD
CMOS input
TTL Schmitt trigger
input
IOH = –2mA
IOL = 4mA
IOH = –6mA
IOL = 4mA
IOH = –8mA
IOL = 8mA
∗5
∗7
∗9
∗10
∗11
(VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Min. Typ. Max. Unit Applicable pins
4.5 5.0 5.5 V
VSS
VDD
V
2.2
V CKI1
0.8
0.7VDD
VDD/2
V
0.5
250k
0.7VDD
2.2
0.3VDD
CKI2
Vp-p
1M 2.5M Ω
V
0.3VDD
∗1
HSYNC,
0.8
V
VSYNC,
SCTR, SCLK,
0.4 SDAT
VDD – 0.8
V
0.4
∗2
VDD – 0.8
V
0.4
∗3
VDD – 0.8
–10
–40 –100
–40
0.4
10
–240
40
V ∗4
∗6
µA ∗8
FLD
–40
40
µA
SHP1A,
SHP2A
58 mA At a 30pF load
∗1 CKLIM, RGTCNT, FRPCNT, CKI3, TEST7, XCLR
∗2 MODE1, MODE2, MODE3, RGT, XRGT, DWN, SHP1B, SHP2B, INV
∗3 VD, BLK, HD, ENB1, ENB2, VCK, VST, PCG, CLP, PRG, FRP, XFRP, XVS, XHS, IRACT, ORACT, HDN
∗4 HST, HCK1, HCK2, RSTR, RCK, RSTW, WCK
∗5 Normal input pins (VIN = Vss or VDD)
∗6 HSYNC, VSYNC, RGTCNT, CKI3, SCTR, SCLK, SDAT, CKI1
∗7 Pins with pull-up resistors (VIN = Vss)
∗8 CKLIM, FRPCNT, TEST7, XCLR
∗9 Bidirectional pins (VIN = Vss or VDD)
∗10 Tri-state (at high impedance, VIN = Vss or VDD)
∗11 VDD = 5.0V, 55MHz input (actual measurement)
–5–
5 Page 
CXD3500R
XCLR pin
The CXD3500R should be forcibly reset during power on in order to initialize the serial transfer block and other
internal circuits. At this time, the serial interface circuit is reset to the initial status (preset status). See page 38
for the preset settings.
Serial transfer operation
1. Control method
The CXD3500R operation timing is controlled by serial data.
The control data is comprised of an 8-bit address and 8-bit data, and the individual data is loaded at the rise of
SCLK. This loading operation starts from the fall of SCTR and is completed at the next rise of SCTR.
Serial transfer timing
SCTR
SCLK
SDAT
D15 D14 D13 D12 D11 D10 D9 D8
Address
D7 D6 D5 D4 D3 D2 D1 D0
Data
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD3500R.PDF ] | |
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