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PDF CXD2728Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2728Q | |
| Descripción | Single-Chip Dolby Pro Logic Surround Decoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2728Q
Single-Chip Dolby Pro Logic Surround Decoder
Description
The CXD2728Q is a CMOS LSI developed for
Dolby Pro Logic Surround. A SRAM for short delay
and AD/DA converters are built in, and all functions
necessary for Dolby Pro Logic Surround such as an
adaptive matrix, a passive decoder including
Modified Dolby B-type NR, auto input balance, a
noise sequencer and center channel mode control
are contained on a single chip. Further, this LSI also
supports Dolby 3 Stereo and Virtual Dolby Surround.
Features
• Dolby Pro Logic Surround decoding with a single
chip
• 2-channel 1-bit AD converter and decimation filter
• 4-channel 1-bit DA converter and oversampling filter
• 32K-bit SRAM for short delay
• No separation or other variance for digital
processing
• External parts reduced due to the built-in AD/DA
converters
Functions
• Adaptive matrix
• Center channel mode control
(Normal/Phantom/Wide)
• Dolby 3 Stereo
• Auto input balance control (ON/OFF)
• Noise sequencer
• Variable delay time (0 to 46.4ms)
• 7kHz low-pass filter (12dB/Oct)
• Modified Dolby B-type NR
• Simple SFC function
• Virtual Dolby Surround
• SFC mode
Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)
• Supply voltage VDD
VSS – 0.5 to +4.6
AVDD ∗1 AVss – 0.5 to + 4.6
V
V
• Input voltage VID VSS – 0.5 to VDD + 0.5 V
∗2 Vss – 0.5 to 5 to Min (VDD + 4.6, 7.0) V
VIA ∗3 AVss – 0.5 to AVD + 0.5 V
• Output voltage VOD VSS – 0.5 to VDD + 0.5 V
∗4 Vss – 0.5 to Min (VDD + 4.6, 7.0) V
VOA ∗3 AVss – 0.5 to AVDD + 0.5 V
• Storage temperature
Tstg –55 to +150 °C
∗1 Analog power supply including AVDX
∗2 Pins 28, 31, 32 and 76
∗3 Analog input/output pin
∗4 Pin 29
80 pin QFP (Plastic)
Recommended Operating Conditions
• Supply voltage VDD 3.0 to 3.6 (3.3 typ.) V
AVDD 3.1 to 3.5 (3.3 typ.) V
Note) Use this IC under the following condition
during the normal operation except for the
power on.
• Supply voltage difference VDD ≤ AVDD + 0.3
V
VSS ≤ AVSS – 0.3
V
• Operating temperature
Ta
–20 to +75
°C
Input/Output Capacitance (VDD = VI = 0V, f = 1MHz)
• Input capacitance CIN
9 (max.)
pF
• Output capacitance COUT
11 (max.)
pF
• Input/output capacitance
CI/O 11 (max.) pF
Maximum Current Consumption
(Ta = 25°C, VDD = 3.6V)
• Digital/analog block total: 75.8mA
Dolby level
• During analog input: 200 to 300mVrms
• During digital input: –20dBFS
Analog Characteristics
Conditions: Pro Logic ON
Measurement at Dolby level = 300mVrms
• S/N: L, Rch = 72dB, C, Sch = 70dB
• THD + N: L, Rch = 0.03%, C, Sch = 0.03%
∗ All values typ.
Structure
Silicon gate CMOS
Applications
Equipment having Dolby Pro Logic Surround
function such as AV amplifiers, receivers and
compact music systems
This device is available only to parties obtaining the license from Dolby Laboratories Licensing Corporation.
"Dolby", the double-D symbol and "Pro Logic" are trademarks of Dolby Laboratories Licensing Corporation.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98Z02-PS
1 page  
CXD2728Q
DC Characteristics
(VDD0 to 2 = 3.0 to 3.6V, AVD1 to 6 = AVDX = 3.1 to 3.5V, AVS1 to 6 = AVSX = VSS0 to 5 = 0V, Ta = –20 to +75°C)
Item
Symbol Conditions
Min. Typ. Max. Unit
Input voltage High level VIH
(1) Low level VIL
CMOS input
0.7VDD
V
0.3VDD V
Input voltage High level VIH
(2) Low level VIL
Schmitt input
0.8VDD
V
0.2VDD V
Input voltage High level VIH
(3) Low level VIL
LVTTL input
2.0
V
0.8 V
Input voltage (4)
VIN Analog input
VSS
VDD V
Output voltage High level VOH IOH = –4.0mA VDD – 0.4
(1) Low level VOL IOL = 4.0mA
V
0.4 V
Output voltage High level VOH
(2) Low level VOL
IOH = –12.0mA
IOL = 12.0mA
VDD/2
VDD/2
V
V
Output voltage (3) Low level VOL IOL = 4.0mA
0.4 V
Input leak current (1)
II VIH = VDD, VSS –10
10 µA
Input leak current (2)
II VIH = VDD, VSS –40
40 µA
Output leak current
IOZ VIH = VDD, VSS –40
40 µA
Feedback resistance
RFB
250k 1M 2.5M Ω
Applicable pins
∗1, ∗2, ∗6, ∗7
∗1, ∗2, ∗6, ∗7
∗5
∗5
∗3
∗3
∗4
∗8, ∗9, ∗13
∗8, ∗9, ∗13
∗11
∗11
∗10
∗1, ∗7
∗2, ∗3, ∗5, ∗6
∗9, ∗10
Resistance between ∗7 and ∗11
∗1 TST0 to TST4, XMST
∗2 XS24, SI
∗3 SCK, XLAT, RVDT
∗4 LIN, RIN
∗5 XRST
∗6 During input to bidirectional pins BCK, LRCK
∗7 XTLI
∗8 During output from bidirectional pins BCK, LRCK
∗9 BFOT
∗10 REDY
∗11 XTLO
∗12 LREF, RREF
∗13 AO1P, AO1N, AO2P, AO2N, AO3P, AO3N, AO4P, AO4N
–5–
5 Page 
CXD2728Q
2-2. When Pro Logic mode is off
Unless otherwise specified, the measurement conditions are as given below.
• Input data = 0dBFS (= 0dB), 1kHz, 16 bits
• Sampling frequency = 44.1kHz
• Measured bands = 10Hz to 20kHz
Item Measurement conditions Channels Min. Typ.
L, R 98
S/N ratio
"A" weighting filter
C
97
S 95
(THD + N)/S∗1
L, R 0.005
C, S 0.003
Dynamic range∗2
"A" weighting filter
L, R
C
97
96
Output level∗3
S 94
(all) 2.01
∗1 See Graphs 2 and 3.
∗2 S/(THD + N) during –60dB input
∗3 The output level depends on the supply voltage (AVDn) as shown in the formula below.
AVDn [V]
Output level [Vrms] = 2.01 [Vrms] ×
3.3 [V]
Max. Unit
dB
%
dB
Vrms
5
2
1
0.500
0.200
0.100
0.050
0.020
0.010
0.005
0.002
0.001
–60 –50 –40 –30 –20 –10
GEN VOLT [dBFS]
0
Graph 2. DAC Characteristics (L, Rch)
5
2
1
0.500
0.200
0.100
0.050
0.020
0.010
0.005
0.002
0.001
–60 –50 –40 –30 –20 –10
GEN VOLT [dBFS]
0
Graph 3. DAC Characteristics (C, Sch)
– 11 –
11 Page | ||
| Páginas | Total 61 Páginas | |
| PDF Descargar | [ Datasheet CXD2728Q.PDF ] | |
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