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PDF CXD2529Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2529Q | |
| Descripción | CD Digital Signal Processor | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2529Q
CD Digital Signal Processor
For the availability of this product, please contact the sales office.
Description
The CXD2529Q is a digital signal processor LSI for
CD players and is equipped with built-in digital filters,
zero detection circuit, 1-bit DAC, and analog low-
pass filter on a single chip.
100 pin QFP (Plastic)
Features
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
– Frame jitter-free
– Allows 0.5 to double-speed continuous playback
– Allows relative rotational velocity readout
– Supports external spindle control
• Wide capture range mode
– Spindle rotational velocity following method
– Supports normal-speed and double-speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals, etc. are output
from a new CPU interface.
• Servo auto sequencer
• Digital audio interface output
• Digital peak meter
Digital Filter, DAC, Analog Low-Pass Filter Block
• DBB (Digital Bass Boost)
• Supports double-speed playback
• Digital de-emphasis
• Digital attenuation function
• Zero detection function
• 8fs oversampling digital filter
• S/N ratio: 100dB or more (master clock: 384fs typ.)
Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384fs typ.)
• Rejection band attenuation: –60dB or more
Applications
CD players
Absolute Maximum Ratings
• Supply voltage
VDD –0.3 to +7.0 V
• Input voltage
VI –0.3 to +7.0 V
(Vss – 0.3V to VDD + 0.3V)
• Output voltage
VO –0.3 to +7.0 V
• Storage temperature Tstg –40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Note) AVDD includes XVDD, and AVSS includes XVSS.
Recommended Operating Conditions
• Supply voltage
VDD 3.4 to 5.25
V
• Operating temperature Topr –20 to +75 °C
Note) The VDD (min.) for the CXD2519Q varies
according to the playback speed selection.
Playback
VDD (min.) [V]
speed
CD-DSP block DAC block
×2
3.4V
4.5V
×1
3.4V
3.4V
× 1∗1
3.4V
∗1 When the internal operation of the CD-DSP
side is set to double-speed mode and the
crystal oscillation frequency is halved,
normal-speed playback results.
Input/Output Capacitances
• Input pin
CI
• Output pin
CO
Note) Measurement conditions
12 (max.) pF
12 (max.) pF
VDD = VI = 0V
fM = 1MHz
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96651A73
1 page  
CXD2529Q
Pin
No.
Symbol
I/O
Description
34 VPCO1 O 1, Z, 0 Charge pump output for wide-band EFM PLL.
35 VCKI
I
VCO2 oscillation input for the wide-band EFM PLL.
36 V16M
O 1, 0 VCO2 oscillation output for the wide-band EFM PLL.
37 VCTL
I
VCO2 control voltage input for the wide-band EFM PLL.
38 PCO
O 1, Z, 0 Master PLL charge pump output.
39 FILO
O Analog Master PLL (slave = digital PLL) filter output.
40 FILI
I
Master PLL filter input.
41 AVSS
— — Analog GND.
42 CLTV
I
Master VCO control voltage input.
43 AVDD
— — Analog power supply (+5V).
44 RF
I
EFM signal input.
45 BIAS
I
Constant current input of the asymmetry circuit.
46 ASYI
I
Asymmetry comparator voltage input.
47 ASYO
O 1, 0 EFM full-swing output (low = VSS, high = VDD).
48 ASYE
I
Low: asymmetry circuit off; high: asymmetry circuit on
49 WDCK O 1, 0 D/A interface. Word clock f = 2fs
50 LRCK
O 1, 0 D/A interface. LR clock output f = fs
51 LRCKI
I
LR clock input.
52 PCMD O 1, 0 D/A interface. Serial data output (two’s complement, MSB first).
53 PCMDI I
D/A interface. Serial data input (two’s complement, MSB first).
54 BCK
O 1, 0 D/A interface. Bit clock output.
55 BCKI
I
D/A interface. Bit clock input.
56 VSS
— — GND.
57 VDD
— — Power supply (+5V).
58 GTOP O 1, 0 GTOP output.
59 XUGF O 1, 0 XUGF output.
60 XPCK O 1, 0 XPLCK output.
61 GFS
O 1, 0 GFS output.
62 RFCK O 1, 0 RFCK output.
63 C2PO O 1, 0 C2PO output.
64 XROF O 1, 0 XRAOF output.
65 MNT3 O 1, 0 MNT3 output.
66 MNT1 O 1, 0 MNT1 output.
67 MNT0 O 1, 0 MNT0 output.
68 XTSL
I
Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz.
69 FSTT
O 1, 0 2/3 frequency-divider output for Pins 89 and 90.
–5–
5 Page 
CXD2529Q
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit Applicable pins
Output voltage
VOUT
1.23∗
Vrms
∗1
Load resistance RL 8
kΩ ∗1
∗ When the sine wave of 1kHz and 0dB is output and it is measured using the circuit shown on the previous
page.
Applicable pins
∗1 LOUT1, LOUT2
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2529Q.PDF ] | |
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