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PDF CXD2310 Data sheet ( Hoja de datos )

Número de pieza CXD2310
Descripción 10-bit 20MSPS Video A/D Converter
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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No Preview Available ! CXD2310 Hoja de datos, Descripción, Manual

CXD2310AR
10-bit 20MSPS Video A/D Converter
Description
The CXD2310AR is a 10-bit CMOS A/D converter
for video applications. This IC is ideally suited for the
A/D conversion of video signals in TVs, VCRs,
camcorders, etc.
48 pin LQFP (Plastic)
Features
Resolution: 10-bit ±1.0 LSB (D.L.E.)
Maximum sampling frequency: 20MSPS
Low power consumption: 150mW (at 20MSPS typ.)
(Not including reference current)
TTL compatible input
Tri-state TTL compatible output (DVDD = 3.3V)
Low input capacitance
Reference impedance: 280(typ.)
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage
VDD
7
Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5
Input voltage (analog) VIN
VDD + 0.5 to VSS – 0.5
Input voltage (digital)
VIH, VIL
VDD + 0.5 to VSS – 0.5
Output voltage (digital) VOH, VOL VDD + 0.5 to VSS – 0.5
Storage temperature
Tstg
–55 to +150
V
V
V
V
V
°C
Recommended Operating Conditions
Supply voltage
AVDD, AVSS
5.0 ± 0.25
DVDD, DVSS
3.0 to 5.25
| DVSS – AVSS | 0 to 100
Reference input voltage VRB
More than 1.8
VRT
to AVDD – 0.4
Analog input
VIN More than 1.8Vp-p
Clock pulse width
TPW1
25 (min.)
TPW0
25 (min.)
Operating ambient temperature
Topr
–20 to +75
V
V
mV
V
V
ns
ns
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95429B5X-PK

1 page




CXD2310 pdf
Pin No.
Symbol
19 TESTMODE
Equivalent circuit
AVDD
19
AVSS
AVDD
20 LINV
20
AVSS
AVDD
21 MINV
18, 25, 26 AVDD
21
AVSS
AVDD
39 VIN
39
AVSS
CXD2310AR
Description
Test mode.
High : Output state
Low : Output fixed
Output inversion.
High : D0 to D8 are
inverted and
output.
Output inversion.
High : D9 is inverted and
output.
Analog VDD.
Analog input.
–5–

5 Page





CXD2310 arduino
CXD2310AR
1. Calibration Function
In order to achieve superior linearity, the CXD2310AR has a built-in calibration circuit. In order to eliminate the
necessity for the externally input calibration pulse required by the earlier CXD2310R, a startup calibration
function and an auto calibration pulse generation function have been newly added to the CXD2310AR. Fig. 1
shows a block diagram of the calibration pulse generation circuit.
CLK
1
16
14 bit
Counter
CLR
AVDD
DQ
CO
CLR
OUT
AVDD
AVSS
VRT
VRB
RESET
CE
Sence
Amp 1
Sence
Amp 2
24 bit
Counter
CLR
CO
SEL
CAL
Fig. 1. Calibration Pulse Generation Circuit
(1) Startup Calibration Function
Over 600 calibration pulses are needed to complete the initial calibration process when the power is first
supplied to the IC. The startup calibration function automatically generates these pulses internally and
completes the initial calibration process.
The following five conditions must be satisfied to initiate the
startup calibration function.
When RESET = High and CE = Low
[V]
AVDD
5
VRT
a) The voltage between AVDD and AVSS is approximately
2.5V or more.
b) The voltage between VRT and VRB is approximately 1V
2.5
0
Sence Amp 1
1V
VRB
[t]
or more.
c) The RESET pin (Pin 15) must is high.
d) The CE pin (Pin 24) must is low.
e) Condition b is met after condition a.
Sence Amp 2
Once all five of these conditions have been met, the calibration
CLR pulses are generated. The pulses are generated by counting 16
main clock cycles on a 14-bit counter and closing the gate when
the carry-out occurs. Therefore, the time required for startup
calibration after the above five conditions have been met is
determined by the following formula:
Startup calibration time = main clock cycle × 16 × 16,384
For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms.
– 11 –

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