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PDF CXD2302Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2302Q | |
| Descripción | 8-bit 50MSPS Video A/D Converter with Clamp Function | |
| Fabricantes | Sony Corporation | |
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CXD2302Q
8-bit 50MSPS Video A/D Converter with Clamp Function
Description
The CXD2302Q is an 8-bit CMOS A/D converter
for video with synchronizing clamp function. The
adoption of 2 step-parallel method achieves low
power consumption and a maximum conversion rate
of 50MSPS.
32 pin QFP (Plastic)
Features
• Resolution: 8 bit ± 1/2LSB (DL)
• Maximum sampling frequency: 50MSPS
• Low power consumption: 125mW (at 50MSPS typ.)
(reference current excluded)
• Synchronizing clamp function
• Clamp ON/OFF function
• Reference voltage self-bias circuit
• Input CMOS/TTL compatible
• 3-state TTL compatible output
• Single 5V power supply or dual 5V/3.3V power supply
• Low input capacitance: 15pF
• Reference impedance: 370Ω (typ.)
Applications
Wide range of applications that require high-speed
A/D conversion such as TV and VCR.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD
7V
• Reference voltage VRT,VRBVDD + 0.5 to Vss – 0.5V
• Input voltage
VIN VDD + 0.5 to Vss – 0.5V
(Analog)
• Input voltage VI VDD + 0.5 to Vss – 0.5V
(Digital)
• Output voltage VO VDD + 0.5 to Vss – 0.5V
(Digital)
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVss 4.75 to 5.25 V
DVDD, DVss 3.0 to 5.5
V
| DVss – AVss | 0 to 100 mV
• Reference input voltage
VRB 0 and above V
VRT 2.7 and below V
• Analog input
VIN
1.7Vp-p above
• Clock pulse width
TPW1, TPW0 9ns (min) to 1.1µs (max)
• Operating ambient temperature
Topr
–40 to +85 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94102E78-PS
1 page  
CXD2302Q
Digital output
The following table shows the relationship between analog input voltage and digital output code.
Timing Chart I
Input signal
voltage
VRT
:
:
:
:
VRB
Step
0
:
127
128
:
255
Digital output code
MSB
LSB
11111111
:
10000000
01111111
:
00000000
TPW1
TPW0
Clock 1.3V
Analog input
Data output
N
N–3
N+1
N–2
N+2
N–1
N+3
N
N+4
N+1
O: Analog signal sampling point
Timing Chart I-1.
tr tf
4ns 4ns
90%
3V
Clock
1.3V
10%
0V
0.7DVDD
Data output
0.3DVDD
tpLH,
tpHL
tr = 4.5ns
OE input
1.3V
tpLZ
Timing Chart I-2.
tf = 4.5ns
90%
10%
tpZL
Output 1
Output 2
10%
tpHZ
90%
1.3V
tpZH
1.3V
Timing Chart I-3.
–5–
3V
0V
VOH
VOL (≠ DVSS)
VOH (≠ DVDD)
VOL
5 Page 
CXD2302Q
2. This IC uses an offset cancel type comparator which operates synchronously with an external clock. It
features the following operating modes which are respectively indicated on the timing chart II with S, H, C
symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.
3. The operation of respective parts is as indicated in the Timing Chart II. For instance input voltage Vi (1) is
sampled with the falling edge of the external clock (1) by means of the upper comparator block and the
lower comparator A block.
The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2).
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to
the upper results. The lower comparator A block finalizes comparison data LD (1) with the rising edge of
the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the
external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital
data output.
Operation Notes
1. VDD, VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital
and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass
to the respective GND’s.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be
prevented by insetting a resistance of about 33Ω in series between the amplifier output and A/D input.
When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect
on the characteristics of A/D conversion.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins
to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VDD and
VRTS, VSS and VRBS respectively, the self-bias function that generates VRT=about 2.5V and VRB=about
0.6V, is activated.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay
of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is
about 9ns (DVDD = 5V).
6. OE pin
Pins 1 to 8 (D0 to D7) are in the output mode by leaving OE open or connecting it to DVSS, and they are in
the high impedance mode by connecting it to DVDD.
– 11 –
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CXD2302Q.PDF ] | |
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