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PDF CXD2064Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2064Q | |
| Descripción | Digital Comb Filter (NTSC/PAL) | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Digital Comb Filter (NTSC/PAL)
CXD2064Q
Description
The CXD2064Q is an adaptive intra-field comb
filter compatible with NTSC and PAL systems, and
can provide high-precision Y/C separation with a
single chip.
48 pin QFP (Plastic)
Features
• Adaptive intra-field Y/C separation
• M-PAL and N-PAL supported
• Vertical enhancer
• Horizontal aperture correction
• 8-bit A/D converter (1-channel)
• 8-bit D/A converter (2-channel)
• 4× PLL
• Sync tip clamp
• Four 1H delay lines
Applications
Y/C separation for color TVs and VCRs
Structure
Silicon gate CMOS ICStructure
Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)
• Supply voltage DVDD VSS – 0.5 to +7.0 V
DAVD VSS – 0.5 to +7.0 V
ADVD VSS – 0.5 to +7.0 V
PLVD VSS – 0.5 to +7.0 V
CLVD VSS – 0.5 to +7.0 V
• Input voltage VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage DVDD
5.0 ± 0.25
DAVD
5.0 ± 0.25
ADVD
5.0 ± 0.25
PLVD
5.0 ± 0.25
CLVD
5.0 ± 0.25
• Analog input ADIN
1.75
• Operating temperature
Topr
–20 to +70
V
V
V
V
V
Vp-p
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96X19B91-PS
1 page  
CXD2064Q
Electrical Characteristics
DC Characteristics
(VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +70°C)
Item
Symbol
Measurement
conditions
Min.
DVDD
DAVD
Supply voltage
ADVD
—
4.75
PLVD
CLVD
Operating temperature
Topr
—
–20
Supply current
IDD Clock 18MHz
—
Input/output voltage
VI, VO
—
Vss
Input voltage
VIH 0.7VDD
CMOS level input
VIL
Input rise/fall time
tr, tf
—
0
Output voltage
IOH = –2mA
VOH
IOH = –3mA
IOL = 4mA
VOL
IOL = 1.5mA
VDD – 0.8
Clock input amplitude
VIN fmax = 50MHz sine wave 0.5
Feedback resistance value RFB VIN = Vss or VDD
250k
Input leak current
IIL, IIH
IIH
VIN = Vss or VDD
VIH = VDD
–10
40
Clock amplifier output delay —
—
3.0
∗1 All pins
∗2 All pins other than ∗6
∗3 All input pins other than ∗6
∗4 All output pins other than ∗5
∗5 CPO (Pin 42)
∗6 FIN (Pin 37)
∗7 All input pins other than ∗8
∗8 Pins 32, 33 and 35
∗9 MCKO (Pin 40)
Typ.
5.0
90
1M
100
9.0
Max.
Unit
Applicable
pins
5.25 V
∗1
+70 °C
— mA
VDD
V
0.3VDD
500
V
ns
V
0.4
2.5M
10
240
18.0
Vp-p
Ω
µA
ns
—
∗2
∗3
∗1
∗4
∗5
∗4
∗5
∗6
∗7
∗8
∗9
–5–
5 Page 
CXD2064Q
Notes on Operation
• Make the wiring for the signal input to ADIN (Pin 2) as short as possible. Also, drive the input signal to ADIN at
low impedance.
• Make the analog and digital power supply and GND lines as wide and short as possible to ensure low
impedance.
• Bypass the analog and digital power supply pins to GND with a ceramic capacitor of about 0.1µF connected
as close to the pin as possible.
• Input a clock that is locked to the burst signal of the input video signal.
• Separate the wiring to the clock input pin FIN (Pin 37) from the external analog circuits, analog power
supplies and analog GND.
• ADIN (analog input signal)
Set the input signal peak-to-peak value VPP to 1.75V or less. Additionally, VPP is recommended to be
1.3V or more since the A/D converter input dynamic range should be made as large as possible.
C→
B→
2.60V (Reference top voltage typical value for internal A/D converter)
VPP
A→
0.67V (Sync tip clamp level)
0.52V (Reference bottom voltage typical value for internal A/D converter)
The DC level at the ADIN pin is as shown in the diagram above when the internal sync tip clamp is used.
Labeling the internal D/A converter AYO output full-scale voltage as VFS, the correspondence
between the ADIN pin voltage and AYO output pin voltage (DC level) is as follows;
DC voltage at point B → AYO maximum output voltage [V]
DC voltage at point A → 0 [V]
DC voltage at point C → VFS [V]
The VFS is the AYO output voltage generated when the voltage equivalent to the point C is input.
• Internal delay
The delay from the internal A/D converter to the D/A converter output is as follows;
NTSC: 1H + 24.5 clocks + αns
PAL: 2H + 24.5 clocks + αns
(α: D/A converter analog output delay = approximately 20ns)
The 24.5 clocks are the sum of the clocks shown below;
A/D converter: 3.5 clocks (“0.5” is for fetching the data at the fall of the clock.)
Internal logic: 20 clocks
D/A converter: 1 clock
– 11 –
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CXD2064Q.PDF ] | |
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