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PDF CXD2053AS Data sheet ( Hoja de datos )
| Número de pieza | CXD2053AS | |
| Descripción | Auto Wide/ EDTV-II ID Detection/ ID-1 Detection | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2053AM/AS
Auto Wide, EDTV-II ID Detection, ID-1 Detection
For the availability of this product, please contact the sales office.
Description
The CXD2053AM/AS is an IC which has the three
functions of identifying the wide video (auto wide),
detecting the EDTV-II ID, and detecting ID-1 (EIAJ,
CPX1024) from the video signal.
CXD2053AM
28 pin SOP (Plastic)
CXD2053AS
28 pin SDIP (Plastic)
Features
• Video aspect ratio identification used with wide
TVs is realized with a single chip.
• I2C bus interface.
This IC can also be used without the bus.
• For auto wide function, 525/60 (NTSC) and 625/50
(PAL, SECAM) can be Supported.
Applications
Wide TV
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD VSS – 0.5 to +7.0
• Input voltage VI VSS – 0.5 to VDD + 0.5
• Output voltage VO VSS – 0.5 to VDD + 0.5
• Storage temperature
Tstg –55 to +150
V
V
V
°C
Recommended Operating Conditions
• Supply voltage VDD
4.5 to 5.5
• Operating temperature
Topr
–20 to +70
V
°C
Block Diagram
ADIN 2
AD Converter
VDIN 11
VSIN 10
Data Slice Sync
Separator
Auto wide
Identification
EDTV-II
ID Decoder
ID-1 Decoder
Timing Signal
Generator
26 OAW1
27 OAW2
28 OED
25 O164
24 OLBX
I2C Bus Interface
15 SCL
16 SDA
19 MCON
22 21
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96531-ST
1 page  
CXD2053AM/AS
Pin
No.
Symbol
Equivalent circuit
9 AVDD
Not connected to VDD (Pin 20) or AVDD
(Pin 1) inside the IC.
12 AVSS
Not connected to AVSS (Pin 3) or VSS
(Pins 17 and 23) inside the IC.
AVDD
Description
Sync separation system analog power supply.
Connect a low-noise power supply from the
digital system.
Sync separation system analog ground.
Connect to the same potential as other VSS
and AVSS.
8 ISET
8
Bias setting.
Connect to AVDD (Pin 9) with 33kΩ.
10 VSIN
11 VDIN
AVSS
AVDD
10
AVSS
AVDD
11
AVSS
Chip clamp, sync separation input.
Input with capacitor coupled.
Clamp voltage 1.5V
Pedestal clamp, ID-1 data slicer input.
Input with capacitor coupled.
Clamp voltage
1.5V
–5–
5 Page 
CXD2053AM/AS
6. Processing of EDTV-II ID and ID-1 data from the bus
EDTV-II ID
or ID-1
Pin direct output
Decoder
Data validity judgment
CXD2053AM/AS
EDVLD or
VBVLD
I2C to microcomputer
As shown in the figure above, the data validity judgment and decoding results are obtained independently
during EDTV-II ID or ID-1 decoding. When outputting these results directly to pins, the results are output after
first taking their logical product (AND). These results are output independently to the I2C bus.
Therefore, processing inside the microcomputer which has acquired the information from the I2C is performed
either by simply outputting this data directly to the pins or by taking the logical product (AND) as above.
In addition, performing the processing when the data validity judgment result (EDVLD or VBVLD) is 1 and the
decoding result is 0 allows video to be judged as 4:3 video. Even video which has had the top and bottom of
the screen blacked out due to picture composition intentions can be viewed as the original 4:3 video by giving
this judgment priority over the auto wide function.
7. Setting EDTV-II ID decoding function
The performance of the EDTV-II ID decoding function can be switched directly by pin settings during either I2C
bus or bus-free mode.
Setting
I2C exists
I2C -free
Resistance to ghosting
Resistance to weak
electric fields
ED2FSC = 0
ED2FSC = 0
ED2FSC = 1
EDDEC2 bit3 = 0, bit2 = 1 EDDEC2 bit3 = 1, bit2 = 0 EDDEC2 bit3 = 1, bit2 = 0
SCL (15pin) = Low
SDA (16pin) = Low
SCL (15pin) = High
SDA (16pin) = Low
SCL (15pin) = High
SDA (15pin) = High
Medium
Strong
Strong
Medium
Medium
Strong
Table 5. EDTV-II ID decoding function switching
ED2FSC is originally a function which stops the 3.58MHz amplitude check for the Y signal input from the S
terminal, etc. However, it can also be used in combination with the EDDEC2 setting to increase the resistance
to ghosting and weak electric fields as shown in the table above. EDDEC2 is the luminance check level
switching during the 3.58MHz or 2.04MHz confirmation signal interval.
Similarly, although EDDEC1 is the 2.04MHz amplitude check level switching, it should be set to bit 5 = 0 and
bit 4 = 1.
Since EDTV-II ID identification for this IC is simple identification, increasing the resistance to weak electric
fields, etc. results in a tradeoff which increases the possibility of misoperation. Accordingly, the leftmost
settings in the table above should be used as the standard settings, and other settings used only when
necessary.
– 11 –
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CXD2053AS.PDF ] | |
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