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PDF CXD1910AQ Data sheet ( Hoja de datos )
| Número de pieza | CXD1910AQ | |
| Descripción | Digital Video Encoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Digital Video Encoder
CXD1910AQ
Description
The CXD1910AQ is a digital video encoder
designed for set top box, digital VCRs and other
digital video applications. The device accepts ITU-
R601 compatible Y, Cb, Cr data, and the data are
encoded to analog composite video and Y/C video
(S-Video) signal.
64 pin QFP (Plastic)
Features
• NTSC and PAL encoding mode
• Composite video and separate Y/C video (S-
Video) outputs
• Y, U, and V outputs
• 8/16-bit pixel data input mode
• 13.5 Mpps pixel rate
• 10-bit 3 channels DACs
• Supports I2C bus (400kHz) and SONY SIO
• Closed Caption (Line 21, Line 284) encoding
• Macrovision Pay-Per-View copy protection system∗
Rev. 6.1
• Monolithic CMOS single 5.0V power supply
• 64-pin plastic QFP package
∗ This device is protected by U.S. patent numbers
4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the Macrovision
anticopy process in the device is licensed by
Macrovision for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Absolute Maximum Ratings
• Supply voltage
VDD –0.3 to +7.0
• Input voltage
VI –0.3 to +7.0
• Output voltage
VO –0.3 to +7.0
• Operating temperature Topr –20 to +75
• Storage temperature Tstg –40 to +125
(Vss = 0V)
V
V
V
°C
°C
Recommended Operating Conditions
• Supply voltage
VDD 4.75 to 5.25
• Input voltage
VIN Vss to VDD
• Operating temperature Topr 0 to +70
V
V
°C
I/O Capacitance
• Input pin
• Output pin
CI 11 (Max.) pF
CO 11 (Max.) pF
Note) Test conditions: VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95235A66-ST
1 page  
CXD1910AQ
Pin
No.
Symbol
52 F1
53 VDD
54 XTEST4
55 XRST
56 SYSCLK
57 PDCLK
58 VSS
59 VSYNC
60 HSYNC
61 SO
62 FID
63 VDD
64 XIICEN
I/O Function
Field ID input.
For external synchronization with XVRST signal, the field for resetting is determined
I by the main signal.
“H” indicates 1st field.
“L” indicates 2nd field.
— Digital power supply
Test mode control input pin. This pin is pulled up.
I When this pin is “H”, the CXD1910AQ is not test mode.
Test mode is available only for device bender.
I
System reset input pin in active low.
When power on reset, set “L” for more than 40 clocks (SYSCLK).
I
System clock input pin.
To generate correct subcarrier frequency, precise 27MHz is required.
Pixel data clock output pin for 13.5MHz.
O This clock is divided from SYSCLK.
This is used when 16-bit pixel data mode.
— Digital ground
O Vertical sync signal output pin.
O Horizontal sync signal output pin.
This pin's function is selected by XIICEN (Pin 64).
O When XIICEN = “H”, this pin is SONY SIO mode; SO serial out output pin.
When XIICEN = “L”, this pin is not used and output is high impedance.
Field ID output pin.
When control register bit “FIDS” = “1”:
O “L” indicates 1st field, “H” indicates 2nd field.
When control register bit “FIDS” = “0”:
“H” indicates 1st field, “L” indicates 2nd field.
— Digital power supply
Serial interface mode select input pin. This pin is pulled up.
I When XIICEN = “L”, Pins 48 to 50 and 61 are I2C-BUS mode.
When XIICEN = “H”, Pins 48 to 50 and 61 are SONY SIO mode.
–5–
5 Page 
CXD1910AQ
2. Serial Interface
The CXD1910AQ supports both I2C-BUS (high-speed mode) and SONY's serial interface. These modes can
be selected by XIICEN input pin as shown in Table 2-1 below.
XIICEN
SI/SDA
SCK/SCL
XCS/SA
SO
H
SONY SIO mode
SI
SCK
XCS
SO
Table 2-1
L
I2C mode
SDA
SCL
SA
High-Z
2-1. I2C-BUS interface
The CXD1910AQ becomes a slave transceiver of I2C-BUS, and supports the 7-bit slave address and the high-
speed mode (400K bit/s).
2-1-1. Slave address
Two kinds of slave address (88H, 8CH) are selectable by the SA signal, as shown in Table 2-2 below.
A6 A5 A4 A3 A2 A1 A0 R/W
1 0 0 0 1 SA 0 X
Table 2-2
2-1-2. Write cycle
S slave address W A start address A
"0"
write data
from master to slave
A write data
AP
from slave to master
D7 D6 D5 D4 D3 D2 D1 D0
start address
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start
address register of this IC as start address of the control register. In subsequent cycles, the data supplied from
the master is written in the addresses indicated by the control register address. The set control register
address is automatically incremented with the completed transfer of each byte of data.
– 11 –
11 Page | ||
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