|
|
PDF CXD1254AQ Data sheet ( Hoja de datos )
| Número de pieza | CXD1254AQ | |
| Descripción | CCD Camera Synchronization and Timing Signal Generator | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CXD1254AQ (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
CXD1254AR/AQ
CCD Camera Synchronization and Timing Signal Generator
Description
The CXD1254AR and CXD1254AQ Ics generates
the necessary synchronization and timing signals for
camera systems employing CCD image sensors
(ICX044, ICX045, ICX046, etc.).
CXD1254AR
64 pin LQFP (Plastic)
CXD1254AQ
64 pin QFP (Plastic)
Features
• Supports color (NTSC) and black & white
(EIA/CCIR) systems
• On-chip electronic shutter
• On-chip horizontal (H) driver
• Timing generator for mirror images
Applications
CCD camera systems
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta=25 °C, VSS=0 V)
• Supply voltage
VSS –0.5 to +7.0 V
• Input voltage
VSS –0.5 to VDD +0.5 V
• Output voltage
VSS –0.5 to VDD +0.5 V
• Operating temperature
–20 to +75 °C
• Storage temperature
–55 to +150 °C
Recommended Operating Conditions
• Supply voltage
4.75 to 5.25
• Operating temperature
–20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E91845B67-TE
1 page  
CXD1254AR/AQ
Pin Description
Pin No.
LQFP QFP
13
24
35
46
57
68
79
8 10
9 11
10 12
11 13
12 14
13 15
14 16
15 17
Pin
HD
VD
CL
D1
D2
D3
TRIG
VSS
OSCI
OSCO
CKIN
ENB
ED0
ED1
ED2
16 18 PS
17 19 AVDD
18 20 H1
19 21 H2
20 22 H3
21 23 H4
22 24 AVSS
23 25 RG
24 26 VDD
25 27 XSUB
26 28 XV2
27 29 XV1
28 30 XSG1
29 31 XV3
30 32 XSG2
31 33 XV4
32 34 VSS
33 35 XSHP
34 36 XSHD
35 37 XSP1
36 38 XSP2
37 39 XDL1
38 40 XDL2
39 41 BFG
40 42 VSS
I/O Function
O Horizontal drive pulse output
O Vertical drive pulse output
O Clock output
NTSC/EIA: 14.318 MHz CCIR: 14.1875 MHz
I Mode selection “Low”: NTSC/EIA “High”: CCIR
(Pull-down resistor)
I Mode selection “Low”: Normal “High”: Mirror
(Pull-down resistor)
I Mode selection “Low”: Color “High”: B/W
(Pull-down resistor)
I Shutter speed setting pulse input
(Pull-up resistor)
— GND for signal generator
I Oscillator input NTSC/EIA: 28.636 MHz CCIR: 28.375 MHz
O Oscillator output
I Input for determining oscillator duty cycle
I Shutter selection “Low”: Normal “High”: Shutter
(Pull-up resistor)
I Shutter speed control
(Pull-up resistor)
I Shutter speed control
(Pull-up resistor)
I Shutter speed control
(Pull-up resistor)
Shutter speed setting data format selection
I
“Low”: Serial “High”: Parallel
(Pull-up resistor)
— Independent power supply for horizontal driver
O Clock output for horizontal register driver
O Clock output for horizontal register driver (Leave open except for ICX046.)
O Clock output for horizontal register driver (Use as H2 except for ICX046.)
O Clock output for horizontal register driver (Leave open except for ICX046.)
— Independent GND for horizontal driver
O Reset gate pulse output
— Power supply for timing generator
O Sensor charge sweep output pulse output
O Clock output for vertical register driver
O Clock output for vertical register driver
O Sensor charge readout pulse output
O Clock output for vertical register driver
O Sensor charge readout pulse output
O Clock output for vertical register driver
O GND for timing generator
O Pre-charge level/sample-and-hold pulse output
O Data sample-and-hold pulse output
O Color separation sample-and-hold pulse output
O Color separation sample-and-hold pulse output
O Pulse output for delay line
O Pulse output for delay line
∗1
∗1
∗1
∗1
∗1
∗1
O Burst flag gate pulse output
— GND for timing generator
—5—
5 Page 
CXD1254AR/AQ
External Synchronization Mode Description
• H Reset
The reset process is started from the first falling edge of the inputted reset pulse. The next reset occurs
only when there is a divergence of at least a clock cycles (0.98 µs) from the edge.
The minimum reset pulse width is 0.98 µs.
The HD output reset position leads the H reset input by 2.45 to 2.94 µs.
H reset input
1H 0.98µs and over
HD output
HD pulse reset at the falling edge of 0.98µs and over
2.45 to 2.94µs
• V Reset
The VD output reset position leads the falling edge of the V reset input by 3.5 to 4.0 H for NTSC/EIA and by
3.0 to 3.5 H for PAL.
The minimum reset pulse width is 32 µs.
V reset input
1V 32µs and over
VD output
3.5 to 4.0H (NTSC/EIA)
3.0 to 3.5H (CCIR)
9H
—11—
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CXD1254AQ.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CXD1254AQ | CCD Camera Synchronization and Timing Signal Generator | Sony Corporation |
| CXD1254AR | CCD Camera Synchronization and Timing Signal Generator | Sony Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |