|
|
PDF CXD1185CR Data sheet ( Hoja de datos )
| Número de pieza | CXD1185CR | |
| Descripción | SCSI 1 Protocol Controller | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CXD1185CR (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CXD1185CQ/CR
SCSI 1 Protocol Controller
For the availability of this product, please contact the sales office.
Description
The CXD1185C is a high performance CMOS
SCSI controller LSI that conforms to ANSIX3. 131-
1986 standards. The CXD1185C is capable of
operating in both initiator and target modes. It
satisfies all standard SCSI bus features, such as
arbitration, selection and parity generation/check
functions. A 24-bit data transfer byte counter and
16-byte FIFO are built into the hardware. Two
separate buses for data and processor makes high
speed data transfer possible. 48 mA (sinking) port
is built-in to achieve reduction in the number of
external components.
The chip offers a set of high level commands at
SCSI phase level. It is also possible to read/write all
individual SCSI signals. The combination of the
above two makes programs simpler and at the same
time improves programmability.
Features
• Satisfies all SCSI bus features, including
arbitration, selection, parity generation/check and
synchronous data transfer.
• Maximum synchronous data transfer rate of 4.0
MB/s and maximum asynchronous data transfer
rate of 2.5 MB/s.
• Provides two separate ports for the data bus and
the CPU bus.
• Built-in user-programmable timer for selection
/reselection time-out operation.
• Supports 8-bit microcomputer bus.
• Support programmed I/O and DMA transfer.
• Built-in 48 mA (sinking) SCSI port. The SCSI port
can be used as either single-ended port or
differential port.
• Built-in 24-bit data transfer counter.
• Built-in 16-byte FIFO.
CXD1185CQ
64 pin QFP (Plastic)
CXD1185CR
64 pin LQFP (Plastic)
• Supports SCSI phase commands.
• All SCSI control signal are software controllable.
• All interrupt conditions are software maskable.
• Built-in 4-bit general-use I/O port.
• Programmable SCSI RST drive time.
• Programmable interrupt pin (IRQ) active logic level.
• Single initiator mode detection logic.
• Selection phase SCSI parity check/ignore switch.
• Pin compatible with CXD1185AQ.
(CXD1185CQ only)
• Comes in 64-pin QFP or 64-pin LQFP
Applications
SCSI controller
Structure
CMOS Process
Absolute Maximum Ratings (Ta=25 °C, VSS=0 V)
• Supply voltage VDD VSS–0.5 to +7.0
V
• Input voltage
VI VSS–0.5 to VDD +0.5 V
• Output voltage VO VSS–0.5 to VDD +0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg –55 to +150 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92905B78-TE
1 page  
CXD1185CQ/CR
Pin No.
CXD1185CQ CXD1185CR
29 27
30 28
31 29
32 30
33 31
34 32
35 33
36 34
37 35
38 36
39 37
40 38
41 39
42 40
43 41
44 42
45 43
46 44
47 45
48 46
49 47
50 48
51 49
52 50
53 51
54 52
55 53
56 54
57 55
58 56
59 57
60 58
Symbol
RES
CS
RE
WE
C7
C6
C5
C4
C3
C2
C1
C0
VSS
IRQ
DRQ
DACK
WED
RED
D0
D1
D2
D3
D4
D5
D6
D7
DP
VSS
CLK
VDD
INIT
TARG
I/O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
61 59 P0 (DOE) I/O
62 60 P1 (ARB) I/O
63 61 P2 (BSYO) I/O
64 62 P3 (SELO) I/O
Description
Reset all registers, negative logic
Chip select signal, negative logic
Internal register read signal, negative logic
Internal register write signal, negative logic
CPU bus bit 7
CPU bus bit 6
CPU bus bit 5
CPU bus bit 4
CPU bus bit 3
CPU bus bit 2
CPU bus bit 1
CPU bus bit 0
GND <note1>
Interrupt request signal
DMA request signal
DMA acknowledge signal, negative logic
Data bus write signal, negative logic <note3>
Data bus read signal, negative logic <note3>
Data bus bit 0 <note3>
Data bus bit 1 <note3>
Data bus bit 2 <note3>
Data bus bit 3 <note3>
Data bus bit 4 <note3>
Data bus bit 5 <note3>
Data bus bit 6 <note3>
Data bus bit 7 <note3>
Data bus parity signal <note4>
GND <note1>
Clock input, 5 –16 MHz
+5 V <note1>
Initiator operation indicator signal
Target operation indicator signal
General-use port bit 0 (SCSI data output authorization)
<note2>
General-use port bit 1 (arbitration in progress) <note2>
General-use port bit 2 (SCSI BSY output)
<note2>
General-use port bit 3 (SCSI SEL output)
<note2>
<Note1> All VDD and VSS pins should be connected to the power supply and ground, respectively.
<Note2> Items in parentheses ( ) indicate the meaning of the signal when operating in the SCSI differential
mode.
<Note3> In systems where the CPU and data buses are not separate, connect the WED and RED pins to
WE and RE, respectively, and Pins D7-D0 to Pins C7-C0.
<Note4> If the data bus parity signal is not used, pull up the DP pin using a resistor.
—5—
5 Page 
CXD1185CQ/CR
Description of Functions
1. Internal registers
The CXD1185C possesses 16 internal registers. The CPU can control the CXD1185C by reading and
writing these registers.
A summary of the registers is provided below.
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Read
Status
SCSI data
Interrupt request 1
Interrupt request 2
SCSI control monitor
FIFO status
SCSI ID
Transfer byte counter (low)
Transfer byte counter (middle)
Transfer byte counter (high)
Interrupt authorization 1
Interrupt authorization 2
Mode
Sync transfer control
SCSI bus control
I/O port
< ∗ > No register assigned to this address.
Write
Command
←
<∗>
Environment setting
Selection/reset timer
<∗>
←
←
←
←
←
←
←
←
←
←
1-1. Status register (R0 : R)
This register is used to monitor the status of the CXD1185C.
76
MRST MDBP
5
4321
INIT TARG TRBZ MIRQ
0
CIP
MRST : Monitors the SCSI bus RST signal, positive logic.
MDBP : Monitors the SCSI bus DBP signal, positive logic.
INIT : “1” when the CXD1185C is in initiator status.
When this bit is set to “1”, commands which are valid in target status and in initiator status are
accepted.
TARG : “1” when the CXD1185C is in target status.
When this bit is set to “1”, commands which are valid in initiator status and in target status are
accepted.
TRBZ : When this bit is set to “1”, it indicates that the transfer byte counter count is zero.
MIRQ : Monitors the interrupt request signal (IRQ signal).
This bit is set whenever interrupt request occurs and cleared once interrupt request 1 register and
interrupt 2 register are read. This bit is not affected by the content of the interrupt authorization
register. The logic level of this bit is not affected by the SIRM bit in the environment setting register.
CIP : Indicates that a chip command is being executed.
While this bit is “1”, no new commands can be written to the command register, with the exception
of the “Reset Chip” command.
—11—
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1185CR.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CXD1185CQ | SCSI 1 Protocol Controller | Sony Corporation |
| CXD1185CR | SCSI 1 Protocol Controller | Sony Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |