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PDF CXA3026Q Data sheet ( Hoja de datos )
| Número de pieza | CXA3026Q | |
| Descripción | 8-bit 120MSPS Flash A/D Converter | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXA3026Q
8-bit 120MSPS Flash A/D Converter
Description
The CXA3026Q is an 8-bit high-speed flash A/D
converter capable of digitizing analog signals at the
maximum rate of 120MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1: 2 demultiplexed output.
48 pin QFP (Plastic)
Features
LEAD TREATMENT: PALLADIUM PLATING
• Differential linearity error: ±0.5LSB or less
• Integral linearity error: ±0.5LSB or less
• High-speed operation with a maximum conversion
Structure
Bipolar silicon monolithic IC
rate of 120MSPS
• Low input capacitance: 21pF
• Wide analog input bandwidth: 150MHz
• Low power consumption: 760mW
• Low error rate
• Excellent temperature characteristics
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• LCDs
• Digital oscilloscopes
• 1: 2 demultiplexed output
• 1/2 frequency divided clock output
(with reset function)
• Compatible with ECL, PECL and TTL digital input levels
• Single +5V power supply operation available
• Surface mounting package
Pin Configuration (Top View)
12 11 10 9 8 7 6 5 4 3 2 1
CLK/E 13
CLKN/E 14
48 RESETN/E
47 RESET/E
CLK/T 15
46 RESETN/T
N.C. 16
45 SELECT
N.C. 17
N.C. 18
DVCC2 19
DGND2 20
P2D0 21
P2D1 22
44 INV
43 CLKOUT
42 DVCC2
41 DGND2
40 P1D7
39 P1D6
P2D2 23
38 P1D5
P2D3 24
37 P1D4
25 26 27 28 29 30 31 32 33 34 35 36
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94711D92
1 page  
CXA3026Q
Pin
No.
Symbol
I/O
Standard
voltage level
15 CLK/T
I
Equivalent circuit
DVCC1
r/2
TTL
46 RESETN/T I
15 46
DGND1
DVEE3
DVCC1
1.5V
r
44 INV
I TTL
44
DGND1
DVEE3
DVCC1
Description
Clock input.
Reset input.
When left open, this input goes to
high level. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
45 SELECT
Vcc
or
GND
45
Data output mode selection.
(See Table 2. Operating Mode
Table.)
11 VRT
9 VRM3
7 VRM2
4 VRM1
2 VRB
DGND1
DVEE3
I
4.0V
(typ.)
VRB +
3 (VRT – VRB)
4
VRB +
2
4
(VRT – VRB)
VRB +
1
4
(VRT – VRB)
I
2.0V
(typ.)
r1
11
r/2
r
Comparator 1
r
9 r Comparator 63
Comparator 64
Comparator 127
7r
Comparator 128
4 r Comparator 191
Comparator 192
r
Comparator 255
r/2
2
r2
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
–5–
5 Page 
When the RESET signal is not used.
CLK
CLK
CXA3026Q
CLK A A
RESETN
CLKOUT
8bits
DATA
CXA3026Q
CLK B B
RESETN
CLKOUT
8bits
DATA
When the RESET signal is used.
CLK
RESET signal
CXA3026Q
CLK A
RESETN
CLK
RESET signal
CLKOUT
8bits
DATA
(Reset period)
CXA3026Q
CLK B
RESETN
8bits
CLKOUT
DATA
(Reset period)
CXA3026Q
2. Straight mode (See Application Circuits 1-(4), (5) and (6).)
Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3026Q supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
RESET signals) level.
Digital input level
ECL
PECL
TTL
DVEE3
–5V
0V
0V
DGND3
0V
+5V
+5V
Supply voltage Application circuits
±5V (1) (4)
+5V (2) (5)
+5V (3) (6)
Table 3. Logic Input Level and Power Supply Settings
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXA3026Q.PDF ] | |
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