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PDF CXA2061 Data sheet ( Hoja de datos )

Número de pieza CXA2061
Descripción Y/C/RGB/D for NTSC Color TVs
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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No Preview Available ! CXA2061 Hoja de datos, Descripción, Manual

Y/C/RGB/D for NTSC Color TVs
CXA2061S
Description
The CXA2061S is a bipolar IC which integrates
the luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC
system color TVs onto a signal chip. The IC also
includes deflection processing functions for wide
TVs.
48 pin SDIP (Plastic)
Features
Reduction in peripheral parts
(ceramic oscillator, AKB sample-and-hold capacitor, etc.)
I2C bus compatible
Built-in deflection compensation circuit which is capable of supporting variaus wide modes
Non-adjusting V oscillator frequency with a countdown system
Non-interlace display support (even/odd selectable)
Non-adjusting Y/C filter
Three sets of CV inputs, two sets of Y/C inputs (can serve as both Y/C and CV inputs), one set of Y/C inputs
supports an external combfilter, two sets of RGB inputs, one set of YUV inputs
It can be outputted YUV on RGB1 inputs
Built-in dynamic picture and dynamic color circuits
Built-in AKB and gamma correction circuits
FSC output
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Abusolute Maximum Ratings (Ta = 25°C, GND1, 2 = 0V)
Supply voltage
VCC1, 2 –0.3 to +12
V
Operating temperature
Topr –20 to +75 °C
Storage temperature
Tstg –65 to +150 °C
Allowable power dissipation PD
1.5 W
(when mounted on a 50mm × 50mm board)
Voltages at each pin
–0.3 to VCC1, 2 + 0.3 V
Operating Condition
Supply voltage
VCC1, 2 9 ± 0.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97538-PS

1 page




CXA2061 pdf
Pin
No.
Symbol
5 V TIM
Equivalent circuit
147
5
25k
CXA2061S
Description
V timing pulse. V timing pulse, HSS and
VSS output can be selected by VTIM SEL
control of the bus.
6 MON OUT
6
200
25.1k
4K
The signal input from TV, CVBS1 and
CVBS2 are selected by VIDEO SEL and
S SEL of the bus and output. In the case
of S terminal input, the luminance signal
and chroma signal are mixed and output.
The output level is 2Vp-p including sync.
7 COMB-C IN
147 10p 25k
7 Input the chroma signal from the comb
filter. Standard input level (burst level) is
25k 0.6Vp-p.
5.4V
8 Y CLAMP
1.5k
8
Capacitor connection for luminance signal
clamp.
Connect to GND via a 0.1µF capacitor.
9 COMB-Y IN
147 25k
9
Input the luminance signal from the comb
filter. The signal is input via a 0.1µF
25k capacitor with a level of 2Vp-p.
(100% white including sync)
5.4V
–5–

5 Page





CXA2061 arduino
Pin
No.
Symbol
40 GND2
41 CVBS2/Y2 IN
Equivalent circuit
147
41
50k
5.4V
CXA2061S
Description
GND (for the signal block circuit).
CVBS signal/luminance signal input.
Input a 1Vp-p (including sync) signal via a
1µF capacitor. When inputting Y/C
separated signals, input the Y signal.
42 ABL FIL
20k
42
1.2k
Connect a capacitor (4.7µF) to GND to form
the LPF of the ABL control signal.
43 TV/C2 IN
44 Vcc2
45 APC FIL
147
43
50k
5.4V
4.9V
1k
45
1k
CVBS signal input from the TV tuner or
chroma signal input.
Input a 1Vp-p (including sync) CVBS signal
or a chroma signal with a burst level of
300mVp-p via a 1µF capacitor.
Power supply
(mainly for the chroma block circuit).
Chroma APC lag-lead filter connection.
Connect CR to GND.
– 11 –

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