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PDF CXA2054S Data sheet ( Hoja de datos )
| Número de pieza | CXA2054S | |
| Descripción | US Audio Multiplexing Decoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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US Audio Multiplexing Decoder
CXA2054S
Description
The CXA2054S is an IC designed as a decoder for
the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in while
adjustment, mode control and sound processor
control are all executed through I2C BUS.
48 pin SDIP (Plastic)
Features
• Audio multiplexing decoder, dbx noise reduction
decoder and sound processor (surround, volume
limiter, bass · treble, volume) are all included in a
single chip. Almost any sort of signal processing is
possible through this IC.
• All adjustments are possible through I2C BUS to
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
parts.
• There are two channel external inputs for LSOUT
outputs.
• Automatic volume control between input sources is
possible through volume limiter.
Standard I/O Level
• Input level
COMPIN (Pin 19)
AUX1-L/R (Pins 40 and 39)
AUX2-L/R (Pins 42 and 41)
SURRIN (Pin 4)
245 mVrms
490 mVrms
490 mVrms
490 mVrms
Pin Configuration (Top View)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VCC 11
• Operating temperature Topr –20 to +75
• Storage temperature Tstg –65 to +150
• Allowable power dissipation
PD 2.2
V
°C
°C
W
Range of Operating Supply Voltage
9±0.5
V
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Structure
Bipolar silicon monolithic IC
• Output level
TVOUT-L/R (Pins 44 and 43)
LSOUT-L/R (Pins 7 and 6)
SURROUT (Pin 5)
490 mVrms
490 mVrms
490 mVrms
∗A license of the dbx-TV noise reduction system is
required for the use this device.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E96Y15B86-TE
1 page  
Pin Pin
Symbol
No. voltage
12 SAD
—
13 MAININ 4.0 V
14 MAINOUT 4.0 V
15 NC
—
16 PCINT1 4.0 V
17 PCINT2 4.0 V
CXA2054S
Equivalent circuit
VCC
12
80k
10k
2V
40k
VCC
10k
VCC
147
13
53k
4V
VCC
VCC ×4
147
14
15k
↓
200µ
1k
15
VCC
147
16
30k
22k
VCC
147
17
10k 10k
2k ×2
4k
—5—
Description
Slave address control switch.
The slave address is selected
by changing the voltage
applied to this pin.
Input the (L+R) signal from
MAINOUT (Pin 14).
(L+R) signal output pin.
—
Stereo block PLL loop filter
integrating pin.
5 Page 
Pin Pin
Symbol
No. voltage
43 TVOUT-R
4.0 V
44 TVOUT-L
Equivalent circuit
VCC
3k
580
43
44 580 147
45 SURRTC 4.0 V
10k
20k
20k
VCC
45
24k
VCC
40k
580
580
CXA2054S
Description
TVOUT right channel output
pin.
TVOUT left channel output
pin.
Set the central frequency of
the SURROUND circuit phase
shifter.
The frequency is determined
by the built-in resistor and the
external capacitance.
(Connect a 0.022 µF capacitor
between this pin and GND.)
—11—
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXA2054S.PDF ] | |
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