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PDF CXA2050S Data sheet ( Hoja de datos )
| Número de pieza | CXA2050S | |
| Descripción | Y/C/RGB/D for PAL/NTSC Color TVs | |
| Fabricantes | Sony Corporation | |
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CXA2050S
Y/C/RGB/D for PAL/NTSC Color TVs
Description
The CXA2050S is a bipolar IC which integrates the
luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for PAL/NTSC
system color TVs onto a single chip. This IC includes
deflection processing functions for wide-screen TVs,
and is also equipped with a SECAM decoder
interface, making it possible to construct a TV
system that supports multiple color systems.
64 pin SDIP (Plastic)
Features
• I2C bus compatible
• Compatible with both PAL and NTSC systems
(also compatible with SECAM if a SECAM decoder is connected)
• Built-in deflection compensation circuit capable of supporting various wide modes
• Countdown system eliminates need for H and V oscillator frequency adjustment
• Automatic identification of 50/60Hz vertical frequency (forced control possible)
• Non-interlace display support (even/odd selectable)
• Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible)
• Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible)
• Non-adjusting Y/C block filter
• One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both
analog and digital inputs)
• Built-in AKB circuit
• Support for forcing YS1 off
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C, SGND, DGND = 0V)
• Supply voltage
SVCC1, 2, DVCC1, 2
–0.3 to +12
V
• Operating temperature
Topr
–20 to +65
°C
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power consumption PD
1.7 W
• Voltages at each pin
–0.3 to SVCC1, SVCC2,
DVCC1, DVCC2 + 0.3 V
Operating Conditions
Supply voltage
SVCC1, 2
DVCC1, 2
9.0 ± 0.5
9.0 ± 0.5
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96403-PS
1 page  
Pin
No.
Symbol
7 SECAMREF
8 SGND1
9 – (R-Y) OUT
10 – (B-Y) OUT
11 YOUT
CXA2050S
Equivalent circuit
Description
6k 20p
SECAM decoder interface. This pin
serves as both a 4.43MHz output and as
7 7.2V a SECAM identification input/output pin.
250µA
— GND for Y/C block.
Color difference signal outputs. Go to
200µA
high impedance when the SECAM
system is detected.
9 Standard output levels for 75% CB:
10 B-Y: 0.665Vp-p
R-Y: 0.525Vp-p
5.7VDC when killer is ON.
500
Luminance signal output.
Black level is 3.5VDC.
11 Standard output level for 100 IRE input:
30k 1Vp-p
400µA
12 SCPOUT
1k Sand castle pulse output. The 0 to 5V
BGP pulse, the phase of which is
12 controlled through the bus, is
superimposed with the 0 to 2V H and
10k
1k
VBLK pulse for output.
13 YRET
13
1.5k
Luminance signal input.
Clamped to 4.8V at the burst timing.
Standard input level for 100 IRE input:
1Vp-p
70k
–5–
5 Page 
Pin
No.
Symbol
52 VSIN
CXA2050S
Equivalent circuit
Description
15k
Sync signal input for V sync separation.
147
52
Input a 2Vp-p Y signal (or a 0.6Vp-p
4.1V sync signal).
20µA
53 HSIN
54 SYNCOUT
55 VM
56 SCL
14k
Sync signal input for H sync separation.
147
53
Input a 2Vp-p Y signal (or a 0.6Vp-p sync
3.2V signal).
10µA
Sync signal output for VSIN and HSIN.
1.2k The output can be selected from the
internal sync signals (Pin 60 or Pin 62) or
147
54
40k
the external sync signal (Pin 63) by the
I2C bus.
Output signal level: 2Vp-p
240µA
(0.6Vp-p sync only)
Input/output gain: 6dB
Outputs the differential waveform of the
VM (Velocity Modulation) Y signal.
500 The signal advanced for 200ns from
1.2k YOUT is output. The delay time versus
147
55
YIN is determined by the DL setting of
30k the I2C bus. This output level can be set
at 2.65Vp-p or 1.1Vp-p by the I2C bus.
400µA
Pedestal level is DC6.2V.
This output can also be turned off by
YS1, YM, and YS2.
4k
56 I2C bus protocol SCL (Serial Clock) input.
VILMAX = 1.5V
VIHMIN = 3.5V
– 11 –
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet CXA2050S.PDF ] | |
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