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PDF CXA2025AS Data sheet ( Hoja de datos )

Número de pieza CXA2025AS
Descripción Y/C/RGB/Sync/Deflection for Color TV
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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CXA2025AS
Y/C/RGB/Sync/Deflection for Color TV
Description
The CXA2025AS is a bipolar IC which integrates
the luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC
system color TVs onto a single chip.
The following functions have been added to the
same function IC, CXA2025S.
1) Vertical sync pull-in speed switching function
2) YUV SW Y signal switching function
Features
I2C bus compatible
Sync signal processing uses a countdown system
with non-adjusting H/V oscillator frequencies
Built-in deflection compensation circuit capable of
supporting various wide modes
Non-adjusting Y/C block filter
Built-in AKB
Video signal I/Os: Y/C separation input, Y/color
difference input, analog RGB input and RGB
output
YUV SW Y signal switching function allows picture
quality adjustment for the Y signal in the same
manner as for the normal Y signal even when
Y/color difference input is selected
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Pin Configuration
48 pin SDIP (Plastic)
Absolute Maximum Ratings
(Ta = 25°C, SGND, JGND = 0V)
Supply voltage
SVCC, JVCC –0.3 to +12 V
Operating temperature
Topr
–20 to +75 °C
Storage temperature
Tstg –65 to +150 °C
Allowable power dissipation
PD 1.5 W
Voltages at each pin –0.3 to SVCC, JVCC + 0.3 V
Operating Conditions
Supply voltage
SVCC
JVCC
9.0 ± 0.5
9.0 ± 0.5
V
V
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96413-ST

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CXA2025AS pdf
CXA2025AS
Pin
No.
Symbol
15 YS
16 RIN
17 GIN
18 BIN
19 RSH
21 GSH
23 BSH
20 ROUT
22 GOUT
24 BOUT
25 IKIN
26
ABLIN
/VCOMP
Equivalent circuit
147
15
40k
SVCC
100µ
Description
YS switch control input.
When YS is high, the RGB block signal is
selected; when YS is low, the Y/C block is
selected.
VILMAX = 0.4V
VIHMIN = 1.0V
VIHMAX = 3.0V
SVCC
200 Analog R, G and B signal input.
Input a 0.7Vp-p (no sync, 100 IRE) signal via a
16 capacitor. The signal is clamped to 5.1V at the
17
18 30k
burst timing of the signal input to the sync input
pin (Pin 44).
SVCC
1k Sample-and-hold for R, G and B AKB.
Connect to GND via a capacitor. When not using
19 AKB (manual cut-off mode), R, G and B cut-off
21 voltage can be controlled by applying a control
23
voltage to each pin. The control voltage is 4.2 ±
50µ 2V.
SVCC
200
12k
20
1100µ
R, G and B signal output.
2.4Vp-p is output during 100% white input.
Input the signal converted from the CRT beam
SVCC
current (cathode current IK) to a voltage via a
1k capacitor. The V blanking part is clamped to 2.7V at
the V retrace timing.
25 The input for this pin is the reference pulse return,
and the loop operates so that the Rch is 1Vp-p and
50µ the G and Bch are 0.83Vp-p. The G and Bch can be
varied by ±0.5V by the bus CUTOFF control. When
not using AKB, this pin should not be connected.
SVCC
147
26
ABL control signal input and VSAW high voltage
fluctuation compensation signal input.
High voltage compensation has linear control
characteristics for the pin voltage range of about
3V to 1V.
ABL does not operate when the pin voltage is 9
[V], and operates with increasing strength as the
voltage becomes lower than 9 [V].
–5–

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