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PDF CXA2000Q Data sheet ( Hoja de datos )
| Número de pieza | CXA2000Q | |
| Descripción | Y/C/RGB/D for PAL/NTSC Color TVs | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXA2000Q
Y/C/RGB/D for PAL/NTSC Color TVs
For the availability of this product, please contact the sales office.
Description
The CXA2000Q is a bipolar IC which integrates the
luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC/PAL
system color TVs onto a single chip. This IC includes
deflection processing functions for wide-screen TVs,
and is also equipped with a SECAM decoder
interface, making it possible to construct a TV
system that supports multiple color systems.
64 pin QFP (Plastic)
Features
• I2C bus compatible
• Compatible with both PAL and NTSC systems
(also compatible with SECAM if a SECAM decoder is connected)
• Built-in deflection compensation circuit capable of supporting various wide modes
• Countdown system eliminates need for H and V oscillator frequency adjustment
• Automatic identification of 50/60Hz vertical frequency (forced control possible)
• Non-interlace display support (even/odd selectable)
• Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible)
• Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible)
• Non-adjusting Y/C block filter
• One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both
analog and digital inputs)
• Built-in AKB circuit
• Support for forcing YS1 off
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C, SGND, DGND = 0V)
• Supply voltage
SVCC1, 2, DVCC1, 2
–0.3 to 12
V
• Operating temperature
Topr
–20 to +65
°C
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipation PD
1.7 W
(when mounted on 50mm × 50mm board)
• Voltages at each pin
–0.3 to SVCC1, SVCC2,
DVCC1, DVCC2 + 0.3 V
Operating Conditions
Supply voltage
SVCC1, 2
DVCC1, 2
9.0 ± 0.5
9.0 ± 0.5
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96103-ST
1 page  
Pin
No.
Symbol
10 SCPOUT
CXA2000Q
Equivalent circuit
Description
1k Sand castle pulse output. The 0 to 5V
BGP pulse, the phase of which is
10 controlled through the bus, is
superimposed with the 0 to 2V H and
10k
1k
VBLK pulse for output.
11 YS1
12 R1IN
13 G1IN
14 B1IN
100µA
YSSW control input.
When YS is high, the RGB1 block signal
is selected; when YS is low, the Y/C block
is selected. This function can be disabled
11 by the YS1OFF setting for the I2C bus.
40k VILMAX = 0.4V
VIHMIN = 1.0V
200 Analog R, G and B signal inputs.
12 Input a 0.7Vp-p (no sync, 100 IRE) signal
13 via a capacitor.
The signal is clamped to 5.7V at the burst
14 timing of the signal input to the HSIN
30k input pin (Pin 47).
15 YS2
100µA
YS/YMSW YS control input.
When YS is high, the RGB2 block signal
is selected; when YS is low, the YSSW
15
40k
output signal is selected.
VILMAX = 0.4V
VIHMIN = 1.0V
16 YM
100µA
YS/YMSW YM control input.
When YM is high, the YSSW output
signal is attenuated by 9.6dB.
16 VILMAX = 0.4V
40k VIHMIN = 1.0V
–5–
5 Page 
Pin
No.
Symbol
51 SDA
Equivalent circuit
CXA2000Q
Description
51 4k I2C bus protocol SDA (Serial Data) I/O.
VILMAX = 1.5V
VIHMIN = 3.5V
VOLMAX = 0.4V
52 BLHOLD
53 CVIN
54 DCTRAN
4k
52
9µA
4.6V
20k
20k 1.2k
Capacitor connection for black peak hold
of the dynamic picture (black expansion).
Composite video signal input.
4.6V Input the 1Vp-p (100% white including
sync) CV signal via a capacitor. The
sync level of the input signal is
53 clamped to 3.8V.
1µA In addition, this pin detects input video
signal HSYNC, and outputs the status
via the status register CVSYNC.
2V
4k 1.2k Connect a capacitor that determines the
54 DC transmission ratio to GND.
2k
55 YIN
4.6V
Y signal input.
Input a 1Vp-p (100% white including
55 sync) Y signal via a capacitor. The
sync level of the input signal is
1µA clamped to 3.8V.
– 11 –
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet CXA2000Q.PDF ] | |
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