PDF CXA1898Q Data sheet ( Hoja de datos )

Número de pieza	CXA1898Q
Descripción	Recording/Playback Equalizer Amplifier
Fabricantes	Sony Corporation
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No Preview Available ! CXA1898Q Recording/Playback Equalizer Amplifier Description The CXA1898Q is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip. 48 pin QFP (Plastic) Features • Recording equalizer Gp and Fp can be adjusted externally. • Recording mute function • AGC (Automatic Gain Control) • Comparator for AMS (Automatic Music Sensor) • Recording/playback equalizer amplifier with 1.7 times speed switching • 11-bit serial data interface Absolute Maximum Ratings • Supply voltage VCC 12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 735 mW Structure Bipolar silicon monolithic IC Applications All analog signal processing in the cassette decks of tape recorders and compact music centers (Applicable to Sankyo Seiki mfg. Co., Ltd. YK47R-KF202 R/P head or equivalent) Operating Conditions Supply voltage VCC 6.5 to 10.0 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94329B78 1 page CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance 17 BPA VDD Equivalent circuit 18 BPB 19 PL1 20 PL2 21 M1 22 M2 5.0V (when reset) (when Pin 25 (DATA) is set to high) O — ×4 10k 17 18 19 × 4 20k 20 GND 21 22 GND Description Outputs D6 from VCC Pin 25 (DATA). Outputs D5 from Pin 25 (DATA). Outputs D4 from Pin 25 (DATA). Outputs D3 from Pin 25 (DATA). Outputs D2 from Pin 25 (DATA). Outputs D1 from Pin 25 (DATA). 23 LATCH 26 XRESET — I 25µA 2k 23 — 26 ×4 5p GND 10.5k GND VCC 100µA 24k Serial data interface latch input. Serial data interface reset input. Low: Reset. At this time serial data outputs (Pins 13 to 22) are all open (high). 24 CLK 25 DATA —I 25µA 4k 24 — 25 ×4 GND 10.5k GND VCC 100µA Serial data interface clock input. 24k Serial data interface serial data input. 32 AGC TC 0.0V — — VCC ×2 VCC ×2 200 500 32 147 ×2 500 5k ×4 100k 200 GND GND Connects a resistor and capacitor for determining AGC attack/recovery time constants. –5– 5 Page CXA1898Q Item Measurement conditions Low level input voltage VIL (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) High level input voltage VIH (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) Low level output voltage VOL, IOL = 2mA (max) (Pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22) High level output off- leak current IOZ Leak current which flows to the output pin when Ioz output is open; applied voltage is 10V. Maximum clock frequency (1) fCK Minimum clock pulse width (2) tWC Minimum reset pulse width (3) tWR Minimum data setup time (4) tSDK (DATA → CLK) Minimum data hold time (5) tHCD (CLK → DATA) Minimum data pulse width (6) tWD Minimum latch setup time (7) tSLD (LATCH → DATA) Minimum latch hold time (8) tHCL (CLK → LATCH) Minimum clock hold time (9) tHLC (LATCH → CLK) Note) • VDD is CPU supply voltage 5.0V. • The maximum value for VDD is Pin 35 (VCC) voltage. • For high level output off leak current, VCC is 10.0V. Min. 0.0 3.5 0.0 — 500 — — — — — — — — Typ. — — — — — — — — — — — — — Max. 1.5 Unit VDD V 0.5 1.0 µA — kHz 1.0 1.0 1.0 1.0 µs 2.0 1.0 1.0 1.0 – 11 – 11 Page

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