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PDF CY7C1021CV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1021CV33 | |
| Descripción | 64K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1021CV33
64K x 16 Static RAM
Features
• Pin- and function-compatible with CY7C1021BV33
• High speed
— tAA = 8, 10, 12, and 15 ns
• CMOS for optimum speed/power
• Low active power
— 360 mW (max.)
• Data retention at 2.0V
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA
Functional Description
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5 64K x 16
A4 RAM Array
A3 512 X 2048
A2
A1
A0
COLUMN DECODER
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021CV33 is available in standard 44-pin TSOP
Type II 400-mil-wide SOJ packages, as well as a 48-ball
FBGA.
I/O1–I/O8
I/O9–I/O16
BHE
WE
CE
OE
BLE
Pin Configuration
SOJ / TSOP II
Top View
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 VSS
33 VCC
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C1021CV33-8
8
95
5
CY7C1021CV33-10
10
90
5
CY7C1021CV33-12
12
85
5
CY7C1021CV33-15
15
80
5
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05132 Rev. *C
Revised October 30, 2002
1 page  
CY7C1021CV33
Switching Characteristics Over the Operating Range[5]
1021CV33-8 1021CV33-10 1021CV33-12 1021CV33-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU[8]
tPD[8]
OE LOW to Data Valid
OE LOW to Low-Z[6]
OE HIGH to High-Z[6, 7]
CE LOW to Low-Z[6]
CE HIGH to High-Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
tDBE Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
Write Cycle[9]
8
3
0
3
0
0
10 12 15 ns
8 10 12 15 ns
3 3 3 ns
8 10 12 15 ns
5 5 6 7 ns
0 0 0 ns
4 5 6 7 ns
3 3 3 ns
4 5 6 7 ns
0 0 0 ns
8 10 12 15 ns
5 5 6 7 ns
0 0 0 ns
4 5 6 7 ns
tWC Write Cycle Time
8 10 12 15 ns
tSCE CE LOW to Write End 7 8 9 10 ns
tAW
Address Set-Up to Write End
7
8
9 10 ns
tHA
Address Hold from Write End
0
0
0
0 ns
tSA
Address Set-Up to Write Start
0
0
0
0 ns
tPWE
WE Pulse Width
6 7 8 10 ns
tSD Data Set-Up to Write End
5
5
6
8 ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[6]
WE LOW to High-Z[6, 7]
0 0 0 0 ns
3 3 3 3 ns
4 5 6 7 ns
tBW
Byte Enable to End of Write
6
7
8
9 ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05132 Rev. *C
Page 5 of 12
5 Page 
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ V34
CY7C1021CV33
44-pin TSOP II Z44
51-85082-*B
51-85087-*A
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05132 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY7C1021CV33.PDF ] | |
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