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PDF CY7C1021 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1021 | |
| Descripción | 64K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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021
CY7C1021
Features
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
— 1320 mW (max.)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1021 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
64K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the write
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021 is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5 64K x 16
A4 RAM Array
A3 512 X 2048
A2
A1
A0
COLUMN DECODER
I/O1 – I/O8
I/O9 – I/O16
BHE
WE
CE
OE
BLE
Pin Configuration
SOJ / TSOP II
Top View
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 VSS
33 VCC
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
1021-2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain preliminary information.
Commercial
Commercial
L
7C1021-10
10
220
5
0.5
7C1021-12
12
220
5
0.5
7C1021-15
15
220
5
0.5
7C1021-20
20
220
5
0.5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05054 Rev. **
Revised August 24, 2001
1 page  
Switching Waveforms (continued)
[12, 13]
Write Cycle No. 1 (CE Controlled)
ADDRESS
CE
tSA
WE
BHE, BLE
DATA I/O
tWC
tSCE
tAW
tPWE
tBW
tSD
Write Cycle No. 2 (BLE or BHE Controlled)
ADDRESS
tWC
BHE, BLE
WE
CE
DATA I/O
tSA tBW
tAW
tPWE
tSCE
tSD
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05054 Rev. **
CY7C1021
tHA
tHD
1021-7
tHA
tHD
1021-8
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY7C1021.PDF ] | |
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