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PDF CY7C1020 Data sheet ( Hoja de datos )

Número de pieza CY7C1020
Descripción 32K x 16 Static RAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY7C1020 Hoja de datos, Descripción, Manual

7C10
CY7C1020
32K x 16 Static RAM
Features
• 5.0V operation (± 10%)
• High speed
— tAA = 10 ns
• Low active power
— 825 mW (max., 10 ns, “L” version)
• Very Low standby power
— 550 µW (max., “L” version)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020 is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
A6
A5
A4 32K x 16
A3 RAM Array
A2
A1
A0
COLUMN DECODER
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020 is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
I/O1 – I/O8
I/O9 – I/O16
BHE
WE
CE
OE
BLE 1020-1
Pin Configuration
SOJ / TSOP II
Top View
NC
A 14
A 13
A12
A11
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A10
A9
A8
A7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A0
43 A1
42 A2
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 VSS
33 VCC
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A3
26 A4
25 A5
24 A6
23 NC
1020-2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
L
L
7C1020-10
10
180
150
3
0.1
7C1020-12
12
170
140
3
0.1
7C1020-15
15
160
130
3
0.1
7C1020-20
20
160
130
3
0.1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 18, 1999

1 page




CY7C1020 pdf
CY7C1020
Switching Waveforms
[8, 9]
Read Cycle No. 1
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
DATA VALID
1020-5
[9, 10]
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V CC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tRC
tHZOE
DATA VALID
tHZCE
tHZBE
HIGH
IMPEDANCE
tPD
50%
1020-6
IICCCC
IISSBB
Notes:
8. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
9. WE is HIGH for read cycle.
10. Address valid prior to or coincident with CE transition LOW.
5

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